Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
2004-07-22
2009-02-17
Shalwala, Bipin (Department: 2629)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S204000
Reexamination Certificate
active
07492341
ABSTRACT:
A semiconductor circuit with the reduced scale of circuitry and a semiconductor integrated circuit chip which is obtained by integrating the semiconductor circuit and enables chip size reduction are provided. For this purpose, a two-decode method is used. The method uses: a pre-decode circuit comprising a first decoder of the preceding stage which decodes an arbitrary bit of an address signal of eight bits and a second decoder of the preceding stage which decodes the remaining bits; level conversion circuits which shift the output of the pre-decode circuit; and post-decode circuits which decode the decode outputs of the decoders in the pre-decode circuit, level-converted through the level conversion circuits.
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Endo Kazuya
Iwasaki Yoshitaka
Sakamaki Goro
Tachibana Toshikazu
Chowdhury Afroza Y
Miles & Stockbridge P.C.
Renesas Technology Corp.
Shalwala Bipin
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