Semiconductor circuit

Details Semiconductor circuit Semiconductor circuit

2002-07-31

2003-11-04

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

C438S449000, C438S282000, C438S232000, C438S154000, C257S276000, C257S376000, C257S370000, C257S379000, C257S511000

Reexamination Certificate

active

06642120

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a semiconductor circuit using the same, which can be applied to a configuration or a circuit which has field transistors and bipolar transistors in combination, for example.
2. Description of the Background Art
FIG. 21
is a circuit diagram showing an example of the configuration of an inverter adopted as a display driver. PMOS transistors Q
1
and Q
3
are cross-coupled. The transistors Q
1
and Q
3
have their drains connected to ground GND through NMOS transistors Q
2
and Q
4
, respectively. A potential Vdd (>0) is given to the sources and back gates of the transistors Q
1
and Q
3
. An input signal SI and a logically inverted version of the input signal SI, obtained through an inverter INV, are given to the gates of the transistors Q
4
and Q
2
, respectively.
Thus, as the input signal SI takes logical “H” and “L,” potentials of approximately zero and Vdd are given to the drains of the series-connected transistors Q
3
and Q
4
, respectively. That is to say, the transistors Q
1
to Q
4
constitute an inverter. Furthermore, since the transistors Q
1
and Q
3
are cross-coupled, the potential at the drains of the transistors Q
3
and Q
4
is stable against the noise carried on the input signal SI.
When the potential Vdd is set at 100 V or higher in the configuration above, it is possible to realize an inverter which provides an output having a transition width of 100 V or more by using the input signal SI having a transition width of several volts. However, setting the potential Vdd so high requires that the transistors Q
1
and Q
3
have increased gate breakdown voltage. For this necessity, a structure with a thicker gate oxide film (a field insulating film, generally), called a field transistor, is adopted to the transistors Q
1
and Q
3
.
FIG. 22
is a cross-sectional view showing the structure of a field transistor
200
which can be adopted as the transistors Q
1
and Q
3
. An N
−
-type semiconductor layer
2
is formed on a P
−
-type substrate
1
and an N
+
-type semiconductor layer
3
is selectively interposed between them. Above the semiconductor layer
3
(on the side opposite to the substrate
1
), field insulating films
8
, P-type semiconductor layers
51
and
52
, and an N-type semiconductor layer
4
are selectively formed in the main surface of the semiconductor layer
2
. The semiconductor layers
51
and
52
face each other with the field insulating film
8
between them and an electrode
9
faces through the field insulating film
8
toward the main surface of the semiconductor layer
2
between the semiconductor layers
51
and
52
.
P
+
-type semiconductor layers
13
and
7
and an N
+
-type semiconductor layer
6
are formed on the top surfaces of the P-type semiconductor layers
51
and
52
and the N-type semiconductor layer
4
, respectively. An electrode
14
is formed on the semiconductor layer
13
and an electrode
10
is connected to the semiconductor layer
7
. The electrode
10
is connected also to the semiconductor layer
6
and conductive to the semiconductor layer
2
that functions the back gate of the field transistor
200
.
When a potential lower than that of the semiconductor layer
2
is applied to the electrode
9
, the conductivity type of the main surface part of the semiconductor layer
2
which faces toward the electrode
9
is inverted to P type. Accordingly, as schematically shown by Arrow
33
, application of a potential higher than that of the semiconductor layer
51
to the semiconductor layer
52
causes holes to move from the semiconductor layer
52
to the semiconductor layer
51
through the main surface of the semiconductor layer
2
. That is, the field transistor
200
functions as a PMOS transistor. The field insulating film
8
interposed between the electrode
9
and the main surface of the semiconductor layer
2
is tens of times thicker than a common gate insulating film, so that the gate breakdown voltage can be set approximately equal to the breakdown voltage between the source and drain.
However, since the field transistor adopts the field insulating film as its gate insulating film, its effective on-state resistance, which is expressed by a product of the on-state resistance and the element area, is extremely poor. Therefore realizing a display driver which is required to provide a large current output further needs common NMOS transistors Q
5
and Q
6
.
The potential Vdd is supplied to the drain of the transistor Q
5
, and the source and back gate of the transistor Q
6
are connected to ground GND. The gate of the transistor Q
5
is connected in common to the drains of the transistors Q
3
and Q
4
and the input signal SI is given to the gate of the transistor Q
6
. The source and back gate of the transistor Q
5
and the drain of the transistor Q
6
are connected in common and an output SO is given from there. However, the gate breakdown voltage of the transistor Q
5
cannot be designed so high as that of the field transistor, so that a protective diode D is needed. Such technique is introduced in, for example, “60V Field NMOS and PMOS transistors for the multi-voltage system integration,” Proceedings of 2001 International Symposium on Power Semiconductor Devices & ICs, pp.259-262.
SUMMARY OF THE INVENTION
The present invention has been made in consideration of the situation shown earlier, and an object of the invention is to provide a semiconductor circuit with high breakdown voltage and large current output, and a semiconductor device applicable to that semiconductor circuit.
According to a first aspect of the present invention, a semiconductor circuit includes P-type first and second field transistors, N-type first and second MOS transistors and an NPN-type first bipolar transistor. The first and second field transistors and the first and second MOS transistors each has a source, a drain and a gate. The first bipolar transistor has a collector, a base and an emitter. A potential is applied to the source of the first field transistor, the source of the second field transistor, and the collector of the first bipolar transistor. This potential is higher than both of a potential applied to the source of the first MOS transistor and a potential applied to the source of the second MOS transistor. The drain of the first field transistor and the drain of the first MOS transistor are connected to the gate of the second field transistor. The drain of the second field transistor is connected to the gate of the first field transistor and the base of the first bipolar transistor. An output signal is obtained at a connection point at which the drain of the second MOS transistor and the emitter of the first bipolar transistor are connected in common. Signals which are complementary to each other are inputted respectively to the gate of the first MOS transistor and the gate of the second MOS transistor.
A large current can be obtained as the output signal because of current amplification by the first bipolar transistor. Furthermore it is not necessary to additionally provide an NMOS transistor together with a protective diode.
Preferably, in the semiconductor circuit, the second field transistor and the first bipolar transistor constitute an insulated-gate bipolar transistor.
Carriers increase because of conductivity modulation, so that a still larger current can be obtained as the output signal.
Preferably, the semiconductor circuit further includes an N-type third MOS transistor. The third MOS transistor has a source, a drain and a gate. A signal is applied to the gate of the third MOS transistor. The signal has a same logic as the signal applied to the gate of the second MOS transistor. The source of the third MOS transistor is connected to the source of the second MOS transistor. The drain of the third MOS transistor is connected, in common, to the gate of the first field transistor, the drain of the second field transistor, and the base of the first bipolar transistor.

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