Semiconductor circuit

Details Semiconductor circuit Semiconductor circuit

2002-03-28

2003-05-06

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Synchronizing

C327S163000

Reexamination Certificate

active

06559695

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a selector apparatus used in a semiconductor circuit apparatus and, more particularly, to a selector apparatus for selecting, according to data provided by a storage, data sent from an element such as a data transfer circuit and outputting the data.
BACKGROUND OF THE INVENTION
FIGS. 6 through 8
show examples of prior-art circuits.
FIG. 8
shows a timing chart.
These prior art circuits are used, for example, in a part of a liquid crystal display device where data to be displayed on a liquid crystal panel is converted.
In
FIG. 6
, a signal S
23
outputted from a storage
601
for storing a first signal S
20
is inputted as a signal S
24
through a decoder circuit
602
into a selector circuit
603
for selecting and outputting one item of data from data appearing on the output signal S
25
of a first flip-flop circuit
604
. The first flip-flop circuit
604
holds a second signal S
21
in synchronization with a third signal S
22
.
An output signal S
26
of the selector circuit
604
is held by a second flip-flop circuit
605
in synchronization with the third signal S
22
, then outputted as an output signal S
27
.
The second flip-flop circuit
605
holds the output signal S
26
of a selector circuit
303
in synchronization with the leading edge of the third signal S
22
in FIG.
8
. The signal held by the second flip-flop circuit
605
is provided as S
27
.
FIG. 7
shows the decoder circuit
602
and selector circuit
603
in an example in which the output signal S
23
of the storage
601
is a 3-bit signal.
In a circuit configuration as shown in
FIG. 6
, the number of circuits of the decoder circuit
602
and selector circuit
603
and therefore the area occupied by them increase as the amount of data handled by the storage
601
increases, resulting in higher chip costs.
The circuit size did not pose the problem in the past because the amount of data handled was relatively small. However, the amount of data handled has increased, the circuit size has become huge and there is the demand for a reduction in circuit size.
It is an object of the present invention to provide a semiconductor circuit apparatus in which an increase in circuit size associated with the increase in the amount of data handled by a storage
601
is small compared with prior-art circuits and therefore the circuit size does not become huge.
DISCLOSURE OF THE INVENTION
A semiconductor circuit apparatus according to the present invention is characterized by replacing a prior-art decoder circuit
602
and selector circuit
603
with a counter circuit, a comparator, and a holder.
According to this configuration, a semiconductor circuit apparatus can be provided in which an increase in circuit size associated with the increase in the amount of data handled by a storage is small and the circuit size does not become huge.
According to claim
1
of the present invention, there is provided a semiconductor circuit apparatus including a selector apparatus selecting and outputting a first serially generated binary signal depending on data held by a first holder, comprising: a second holder for holding the first signal in synchronization with a second signal; a counter circuit for performing a count operation in synchronization with the second signal; a comparator for comparing an output signal of the counter circuit with the data held by the second holder; a selector circuit for selecting and outputting either a signal held by the second holder or another, predetermined timing signal depending on the binary level of a timing signal indicating timing when a match is detected by the comparator means; third hold means for holding an output signal of the selector circuit in synchronization with a third signal; and fourth hold means for holding data held in the third hold means in synchronization with a fourth signal; wherein data held in the third hold means is provided as the predetermined timing signal to the selector circuit and a signal held by the fourth hold means is provided as an output signal.
According to claim
2
of the present invention, there is provided a semiconductor circuit apparatus in which a selector apparatus selecting and outputting a first serially generated binary signal depending on data held by first hold means is provided, comprising: second hold means for holding the first signal in synchronization with a second signal; a counter circuit for performing a count operation in synchronization with the second signal; comparator means for comparing an output signal of the counter circuit with data held in the second hold means; third hold means for holding the data held in the second hold means in synchronization with a timing signal indicating timing at which the comparator means detects a match; and fourth hold means for holding a signal held in the third hold means in synchronization with a third signal, wherein a signal held in the fourth hold means is provided as an output signal.


REFERENCES:
patent: 4224671 (1980-09-01), Sugiyama et al.
patent: 5684418 (1997-11-01), Yanagiuchi
patent: 5821781 (1998-10-01), Rigazio

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