Miscellaneous active electrical nonlinear devices – circuits – and – Specific signal discriminating without subsequent control – By amplitude
Reexamination Certificate
1998-09-11
2001-02-27
Lam, Tuan T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Specific signal discriminating without subsequent control
By amplitude
C327S089000, C327S563000
Reexamination Certificate
active
06194920
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit, and more particularly to a semiconductor circuit which is used as an input buffer for interconnection between large scale integration circuits.
2. Description of the Related Art
As a semiconductor circuit of the type mentioned, a differential amplification circuit is conventionally used to achieve a high speed interface operation.
An NMOS differential amplification circuit which employs an NMOS transistor amplifies, if a signal of a false emitter coupled logic (ECL) level is applied to an input terminal, the signal and outputs a signal of a complementary metal oxide semiconductor (CMOS) level (hereinafter referred to as first prior art).
The circuit of the first prior art described above exhibits a small delay when the level of the input signal is proximate to a power supply voltage like a signal of the false ECL level. However, the first prior art circuit is disadvantageous in that, when the level of the input signal is proximate to a reference voltage like a gunning transfer logic (GTL) level, it exhibits a large delay time because the operating current is low.
Meanwhile, a PMOS differential amplification circuit which employs a PMOS transistor receives a signal of the GTL level at an input terminal thereof and outputs a signal of the CMOS level (hereinafter referred to as second prior art).
The circuit of the second prior art just described exhibits a small delay time when the level of the input signal is proximate to the GTL level. However, the second prior art circuit is disadvantageous in that it exhibits a large delay time when the level of the input signal is proximate to a power supply voltage like a signal of the false ECL level.
A further semiconductor circuit of the type described is disclosed in Japanese Patent Laid-Open Application No. Heisei 5-48430 and is shown in FIG.
7
.
Referring to
FIG. 7
, the semiconductor circuit includes a PMOS differential circuit
1100
and an NMOS differential circuit
1200
whose output terminals are connected to an output line
1140
. A pair of inverters
1150
and
1160
are connected in a cascade connection to the output line
1140
so that an output signal may be obtained through the inverters
1150
and
1160
(hereinafter referred to as third prior art).
Referring also to
FIG. 8
, with the semiconductor circuit of the third prior art, since the output terminal of the PMOS differential circuit
1100
and the output terminal of the NMOS differential circuit
1200
are connected to the output line
1140
, even if a signal which oscillates between the ground level GND and a power supply voltage is inputted to each of the input terminals, the signal outputted from the output line
1140
does not exhibit oscillations between the ground level and the power supply voltage. Consequently, the semiconductor circuit is disadvantageous in that, in the inverter
1150
connected to the output line
1140
, through-current flows from a power supply terminal to the ground and increases the power dissipation as much.
Further, since also the output signal of the inverter
1150
does not oscillate between the ground level and the power supply voltage, it must be inputted to the additional inverter
1160
. In this manner, the third prior art circuit is disadvantageous in that, in order to obtain an output signal which oscillates between the ground level and the power supply voltage, an additional inverter must be provided and this has a bad influence on high speed operation.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor circuit which can accept signals of various levels and operate at a high speed with low power dissipation.
It is another object of the present invention to provide a semiconductor circuit which outputs a signal which oscillates between the ground level and a power supply voltage when a signal which oscillates between the ground level and the power supply voltage like a CMOS level signal is inputted.
It is a further object of the present invention to provide a semiconductor circuit which can correct a displacement of a CMOS level signal inputted thereto from a threshold level.
In order to attain the object described above, according to the present invention, there is provided a semiconductor circuit, comprising first and second input terminals, a PMOS differential circuit having two inputs one of which is connected to the first input terminal and the other of which is connected to the second input terminal for outputting a first differential output, an NMOS differential circuit having two inputs one of which is connected to the first input terminal and the other of which is connected to the second input terminal for outputting a second differential output, first and second power supply terminals, an output terminal, and an output circuit operable in response to the first and second differential outputs for preventing, when a current path is formed between the output terminal and the first power supply terminal, formation of a current path between the second power supply terminal and the output terminal, but preventing, when a current path is formed between the output terminal and the second power supply terminal, formation of a current path between the first power supply terminal and the output terminal.
In the semiconductor circuit, the output circuit is provided which operates in response to differential outputs of the PMOS differential circuit and the NMOS differential circuit such that, when a current path is formed between the output terminal and the first power supply terminal, it prevents formation of a current path between the second power supply terminal and the output terminal, but, when a current path is formed between the output terminal and the second power supply terminal, it prevents formation of a current path between the first power supply terminal and the output terminal. Consequently, when a CMOS level signal which oscillates between potentials of the first and second power supply terminals is inputted, the semiconductor circuit can output a CMOS level signal which oscillates between the potentials of the first and second power supply terminals. Consequently, the semiconductor circuit can accept signals of various levels and operate at a high speed with low power dissipation.
The output circuit may include a first PMOS transistor having a control terminal to which the first differential output of the PMOS differential circuit is inputted, and a source connected to the first power supply terminal, a second PMOS transistor having a control terminal to which the second differential output of the NMOS differential circuit is inputted, a source connected to a drain of the first PMOS transistor, and a drain connected to the output terminal, a first NMOS transistor having a control terminal to which the first differential output of the PMOS differential circuit is inputted, and a drain connected to the output terminal and the drain of the second PMOS transistor, and a second NMOS transistor having a control terminal to which the second differential output of the NMOS differential circuit is inputted, a drain connected to a source of the first NMOS transistor, and a source connected to the second power supply terminal.
As an alternative, the output circuit may include a first PMOS transistor having a control terminal to which the second differential output of the NMOS differential circuit is inputted, and a source connected to the first power supply terminal, a second PMOS transistor having a control terminal to which the first differential output of the PMOS differential circuit is inputted, a source connected to a drain of the first PMOS transistor, and a drain connected to the output terminal, a first NMOS transistor having a control terminal to which the first differential output of the PMOS differential circuit is inputted, and a drain connected to the output terminal and the drain of the second PNOS transistor, and a second NMOS transistor having a control
Foley & Lardner
Lam Tuan T.
NEC Corporation
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