Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Clock or pulse waveform generating
Reexamination Certificate
1999-06-29
2001-04-24
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Clock or pulse waveform generating
C327S144000
Reexamination Certificate
active
06222410
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor circuit which has a plurality of transmission paths and in which transmission elements having smaller amounts of delay are arranged in the transmission paths that have a smaller value than the absolute value of the threshold voltage set.
2. Description of the Related Art
In recent years, semiconductor circuits have generally adopted the technique of lowering the power supply voltage VDD for lowering the power. In order to compensate for the deterioration of a transmission rate due to the reduction of the voltage, the transfer gates serving as the transmission elements arranged in each transmission interconnection path and the transistors constituting the logic circuits are being made low threshold voltage transistors having a lower threshold voltage Vth than that of usual transistors. In general, the speed v and the power supply voltage VDD satisfy the following relationship:
v∝VDD/(VDD−Vth)
A
(1)
Here, A is a coefficient affected by speed saturation and is 1 to 2.
As seen from equation (1), by making the threshold voltage Vth small, the decline in the speed can be alleviated even if the power supply voltage VDD is lowered.
Summarizing the problem to be solved by the invention, the sub threshold leakage current I
L
of a transistor is abruptly increased by a reduction of the threshold voltage Vth of the transistor as represented by the following equation (2):
I
L
∝exp(−Vth/S) (2)
Here, S is a sub threshold swing and is generally about 80 mV/dec.
In the related art, this low threshold voltage transistor was used over the entire semiconductor chip or over a considerably wide range of the same. The larger the size of the chip, therefore, the larger the number of the low threshold voltage transistors causing leakage. This leakage current has become a problem from a viewpoint of the power.
For example, “IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996” and “IEEE Journal of Solid-State Circuits, Vol. 32, No. 11, November 1997” reported that the leakage current can no longer be ignored even during operation, for example, the leakage power becomes 20 mW in a maximum power of 450 mW and the leakage power becomes 4 mW for an active power of 17 mW.
For this reason, there may be cases where it becomes necessary to take measures like, as reported in for example “IEEE Journal of Solid-State Circuits, Vol. 30, No. 8, August 1995”, suppressing the leakage current in the stand-by state by inserting a switch of a high threshold voltage transistor in series in a low threshold voltage transistor circuit and separating them in the stand-by state to reduce the leakage current or, as reported in “ISSCC95/Session 19/Technology Directions: Quantum Computing & Low-Power Digital”, controlling the substrate bias to increase the threshold voltage in the stand-by state and thereby suppressing the leakage current.
Further, since low threshold voltage transistors have been used over a wider range than necessary in the related art, there was a fundamental problem that since low threshold voltage transistors were used even in a groups of paths having a fast speed and a small delay not requiring improvement of speed and away from critical paths, an unnecessarily large leakage current was generated.
This problem will be further explained with reference to the drawings.
FIG.
11
and
FIG. 12
are views conceptually showing the delay distribution in delay transmission paths, or “delay paths”, when making full use of transmission elements comprising low threshold voltage transistors. In the figures, the abscissas indicate the delay values, and the ordinates indicate the delay distribution. Further, in the figures, “1” denotes the delay distribution before lowering the threshold voltage, “2” denotes the delay distribution after lowering the threshold voltage, “3” denotes the maximum delay value before lowering the threshold voltage, and “4” denotes the maximum delay value, an improved value of the maximum delay value, after lowering the threshold voltage. As shown in
FIG. 11
, when lowering the threshold voltage, the speed is raised over the entire delay path.
However, the region in which the speed is faster than the improved value 4 of the maximum delay value is a part where it is meaningless speed-wise to use a low Vth to raise the speed.
Namely, the hatched part in
FIG. 12
is a region where the speed is unnecessarily raised, that is, leakage is unnecessarily generated.
In this way, a means has been sought for efficiently suppressing an increase of the leakage current when using low threshold voltage transmission elements in the delay paths so as to lower the power and voltage.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor circuit capable of keeping the leakage current to a minimum while drawing out the maximum effect of improvement of the speed due to a reduction of the threshold voltage.
According to a first aspect of the present invention, there is provided a semiconductor circuit having a plurality of transmission paths, each transmission path having arranged in it at least one transmission element with a smaller amount of delay that is smaller than an absolute value of a set threshold value, wherein at least part of at least one transmission path among the plurality of transmission paths is arranged so that a low threshold voltage transmission element with an absolute value of the threshold voltage smaller than that of the other transmission elements.
Preferably, the low threshold transmission element is arranged in at least the transmission path with the largest delay value.
Preferably, the delay transmission paths to which the low threshold voltage transmission elements are applied are limited to the delay transmission paths in the range of delay from the maximum delay value before arrangement of the low threshold voltage transmission elements to about the permissible maximum value in a case where the low threshold voltage transmission elements are applied.
Preferably, a repeater buffer is inserted into a delay unit where a delay more than a predetermined value based on the interconnection resistance and the interconnection capacitance exist.
According to a second aspect of the present invention, there is provided a semiconductor circuit comprised of a plurality of functional units having arranged in it at least one transmission element with a smaller amount of delay the smaller than an absolute value of a set threshold value, wherein the threshold voltage of the transmission element in at least one functional unit is set to a lower threshold voltage than the transmission elements of other functional units.
Preferably, at least the substrates of functional units to be lowered in threshold voltage are isolated from the substrates of other functional units and the substrate potential of the functional units to be lowered in threshold voltage is adjusted to become lower than the normal threshold voltage.
Preferably, the functional units where the threshold voltages of the transmission elements are set to lower threshold voltages than the transmission elements of other functional units comprise transmission paths having delay value larger than the delay value of the transmission paths of the other function units.
According to the present invention, by applying a low threshold voltage over a limited range of application, the leakage current can be kept to a minimum while drawing out the maximum effect of improvement of the speed due to the reduction of the threshold voltage.
The range of application is the range from the maximum delay value before the lowering of the threshold voltage to the delay value improved by lowering the threshold voltage of the delay transmission path or the new maximum delay value when lowering the threshold voltage by a slower amount.
The threshold voltage is lowered at the transistor or cell level of the delay transmission path. As a result, there is the effect that it is
Kananen Ronald P.
Nguyen Linh
Rader Fishman & Grauer
Sony Coorporation
Tran Toan
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