Active solid-state devices (e.g. – transistors – solid-state diode – Bipolar transistor structure – With enlarged emitter area
Reexamination Certificate
1998-12-07
2001-10-16
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Bipolar transistor structure
With enlarged emitter area
C257S582000, C257S690000, C257S698000, C257S699000, C257S704000, C257S705000, C257S706000, C257S707000, C257S708000, C257S719000, C257S723000, C257S732000
Reexamination Certificate
active
06303974
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the encapsulation of semiconductor chips, such as the encapsulation of a plurality of insulated gate bipolar transistor (IGBT) chips in a single housing of the double-side-cooled type with the option of including other components such as an anti-parallel diode and/or resistive connecting paths.
BACKGROUND OF THE INVENTION
An IGBT device has a highly complex fine geometry structure that effectively limits the size of a single IGBT chip which can be processed with an acceptable yield. Where an IGBT device of larger size is required it may be produced from an assembly of chips encapsulated in a single unit. In the main, such units have been produced in a single-side-cooled arrangement where the chips are mounted on a thermally and electrically conducting base plate or stud constituting an anode terminal and cooling contact. The emitter and gate leads are connected in common to their respective electrodes in a header seal. In order to avoid undesirable interaction between the separate chips, the connection from the common gate point to each individual chip characteristically includes a ballast resistance in its path. The inductive loop between emitter and gate leads is also desirably kept to a minimum.
To maximise the useful current rating of silicon power devices, especially diodes, thyristors and gate turn-off thyristors and to provide efficient cooling together with greater flexibility of application it has become common practice to provide disc-like encapsulations (sometimes known as the “hockey-puck” style) which may be cooled from either or both of the pole-pieces constituting the main current electrodes. The structure of such a device encapsulation is described in “Thyristor Design and Realization” by P. D. Taylor (Wiley, 1987)—see p.208 and FIG. 6.7 of the 1992 paperback edition. There are similar advantages to the user when IGBT devices are encapsulated likewise. EP-A-0 702 406 shows such a device incorporating a plurality of IGBT chips. However the internal connections shown therein, particularly those relating to distribution of the gate signal, are complex and imply potential difficulties for manufacturers seeking to offer devices in this form. There may also be mentioned as prior art EP-A- 0 773 585 and EP-A- 0 746 023.
SUMMARY OF THE INVENTION
According to the present invention from one aspect, there is provided a semiconductor device comprising, in a housing:
a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the housing; and
electrically conductive contact pin arrangements projecting from electrically insulated channels in the preformed sub-assembly, an inward end of each of said pin arrangements being so arranged, when urged into its channel, as to provide an electrical connection to a part of the surface of a semiconductor chip, wherein:
there is a sheet of electrically conductive material, resting in recesses on the inner surface of the emitter electrode and electrically isolated therefrom by an electrically insulating insert, as a means for distributing an electrical signal and making simultaneous contact with the opposite ends of said pin arrangements.
The channels and the pin arrangements may be such that the pin arrangements are out of contact with the semiconductor chips when the preformed sub-assembly is not supported on a surface which interacts with the opposite ends of said pin arrangements.
The housing may be of the double-side-cooled type.
The emitter electrode may have a first, outer planar face and an opposing, inner surface comprising pillars of material delineated by recesses formed on the inner surface of the electrode, the walls of the pillars being substantially at right angles to the outer face of the emitter electrode and the top faces of the pillars being coplanar and substantially parallel to the first, outer face. The recesses may all be formed to the same depth to define a uniform base level on the inner side of the emitter electrode.
Said pre-formed sub-assembly may include a preform of electrically insulating material and contain apertures to accommodate the pillars so that it can be lowered thereover, the preform being of such height that, when finally assembled, it stands a little higher than the tops of the pillars and being also provided with a shallow recessed central area essentially level with the tops of the pillars.
Said channels may be in the insulating preform and run parallel and close to the walls of the pillars.
An electrically conductive retaining shim may be positionally located in the central recessed area of said preform and apertured so as not to obstruct or occlude the ends of said channels.
An electrically insulating frame with rebated windows may be positioned so that the window apertures correspond generally to the lateral boundaries of the pillars but are extended to include the vertical projections of the channels, an electrically conductive buffer shim and one of the semiconductor chips being serially located in each window aperture and window rebate respectively to rest on the retaining shim above the top surface of a respective one of the pillars so as to present said part of the surface of the semiconductor chip toward the inward end of the conductive contact pin arrangement occupying the respective channel.
A thermally and electrically conducting buffer plate may be arranged to overlie and contact the upper faces of all such semiconductor chips.
A collar clip may captivate the retaining shim, the buffer shims, the semiconductor chips and the buffer plate in the preform.
The semiconductor chips may be of a mixture of types, e.g. IGBT chips and diode chips with the contact pin arrangements being applied only to those requiring them.
The emitter and anode electrodes may be provided with metal flanges to one of which is attached an insulating collar with a further flange joined (e.g. by welding) to the flange on the other main electrode so that all the assembled parts are sealed in an hermetic capsule forming the housing. The common electrical signal or gate point may be at the inner end of a lead-through conductor set in the wall of the insulating collar and electrically attached to the conductive sheet, the outer end of the lead-through conductor being for the signal or gate electrode of the device.
Other modifications or additions to the overall structure may also be made. The emitter electrode may be in two parts, the first carrying the insulating collar and the second carrying the pillars. By this means the material of the second part of the emitter electrode may be chosen so that the lateral distance separating the pillars is constrained to expand thermally at a rate nearer to that of a buffer plate overlying the semiconductor chips. Each contact pin arrangement may incorporate its own means of springing to make resilient contact with both the sheet of conductive material and its associated semiconductor chip or alternatively the sheet may incorporate such means of resilience to urge a contact pin arrangement into contact with its chip.
The conductive sheet may have included within or attached to its structure resistors lying in the respective paths to each contact pin arrangement or a resistor may be incorporated within the structure of each contact pin arrangement or a resistor may be incorporated within or attached to the structure of each contact pin arrangement contacted semiconductor chip.
According to the present invention from another aspect, there is provided a semiconductor device comprising, in a housing:
a plurality of semiconductor chips captivated in a preformed sub-assembly and arranged to present contact areas for connection to anode and emitter electrodes of the housing; and
electrically conductive contact pin arrangements projecting from electrically insulated channels in the preformed sub-assembly, an inward end of each of said pin arrangements being so arranged, when urged into its channel, as to provide an electrical co
Billett Kevin Robert
Evans Michael John
Irons Robert Charles
Christie Parker & Hale LLP
Lee Eddie
Warren Matthew E.
Westcode Semiconductors Limited
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