Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-05-23
2003-12-30
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S222000, C365S201000, C365S236000, C327S113000
Reexamination Certificate
active
06671221
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor chip, particularly a semiconductor chip with at least one oscillator for controlling internal functions.
A number of oscillators are often implemented on semiconductor chips (known as ICs) and employed for various functions. Typical applications of the oscillators are voltage pumps or what is known as self-refresh control in DRAM memories (hereinafter DRAMs). In finished chips, the frequencies of the oscillators exhibit a particular distribution that is the unavoidable result of production-related parameter fluctuations. In order to reduce the distribution ranges and generate an identical (that is to say, controlled) frequency for all chips, the oscillators must be set to their assigned frequency in the context of a test program, with which the functionality of the semiconductor chip is otherwise tested. An important instance of application in this regard is the oscillator for the self-refresh control on a DRAM. Here, sharp frequency deviations lead either to an elevated standby power consumption or even to failure of individual memory cells, which is known as retention failure.
The aforementioned test program is usually executed at an early point in chip production, typically on the wafer plane. In the case of a self-refresh oscillator of a DRAM, the setting of the oscillators, also known as trimming, occurs on the wafer plane in that the oscillator signal is driven out at a chip terminal (I/O) by activation of a suitable test mode. An external test device is provided in order to measure the oscillator signal and determine the instantaneous frequency of the oscillator signal. The semiconductor chip, in this case the semiconductor memory (DRAM), is typically provided with an internal logic, which allows the modifying or trimming of the frequency of the oscillator. On the basis of the measured frequency, correction information is calculated, which can be stored in a non-volatile fashion on the chip by fuses (a laser fuse or electrical fuse—hereinafter E-fuse). In order to increase the accuracy of the oscillator frequency trimming, the correction value for the frequency that is obtained in a first measuring step must be programmed as a trial value into the step that is to be tested. In a new frequency measuring step, it is then checked whether the frequency is sufficiently near the desired value, or whether additional fine corrections are needed.
This type of oscillator frequency trimming with the aid of an external testing device is time-consuming and must be performed for each chip individually in certain circumstances. Besides this, frequency measuring on a typically digital testing device is only possible at great cost and with long test times.
In principle, it is possible to measure the oscillator frequencies of a number of chips in a parallel fashion and not to verify an ascertained correction address at the relevant chip. But this leads to a loss of precision and thus to losses in yield and lower quality.
The high testing outlay cannot be overcome by a parallel test sequence. The reason is that each chip must be corrected individually, and therefore time cannot be gained by parallel testing. In light of the fact that wafer tests are otherwise being increasingly conducted in parallel fashion, this circumstance leads to a rising proportion of the test outlay being expended in trimming the oscillator frequency. Particularly in light of the full wafer test, i.e. the parallel testing of the whole wafer, which has been discussed though not yet implemented, the exceptional position of frequency trimming leads to a prolongation of the test time, which is associated with high costs. German Patent DE 692 26 656 T2 teaches a semiconductor chip, particularly a semiconductor memory, with at least one oscillator for controlling internal functions, whereby a circuit for automatically trimming the frequency of the oscillator is implemented on the semiconductor chip.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor chip with a trimmable oscillator that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which guarantees the parallel setting of the oscillator frequency for a plurality of semiconductor chips without losses in yield or quality.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor chip, in particular a memory chip. The semiconductor chip contains at least one oscillator for controlling internal functions and generates an oscillator signal with an oscillating frequency. A trimming circuit is connected to the oscillator for automatically trimming the oscillating frequency of the oscillator. The trimming circuit receives and is driven by an external clock signal having a clock frequency higher than the oscillator frequency. The trimming circuit contains a counter for measuring the oscillator frequency and a trimming logic circuit for comparing the oscillator frequency measured to a desired frequency. The trimming logic circuit outputs a trim command to the oscillator corresponding to a difference between the oscillator frequency measured by the counter and the desired frequency.
With the integration of the trimming circuit on the semiconductor chip, the high outlay that has been required in connection with the utilization of an external testing device to detect and set the oscillator frequency is eliminated, because the process can be carried out on the semiconductor chip itself. The inventive approach thus simplifies the external test program specifically for semiconductor chips on the wafer plane, because the overall testing program, including the test of the oscillator frequency, can run parallel with the other steps.
Another advantage of the inventive trimming circuit that is integrated on the semiconductor chips is that the time required for trimming the oscillator frequency, and with this the testing costs, can be reduced. The time and cost savings are greater the more semiconductor chips are tested in parallel fashion.
Because the external testing device for testing the semiconductor chip specifically on the wafer plane no longer has to be laid out to measure frequencies, corresponding auxiliary equipment that is required for this can be omitted. This is essential particularly in view of the high degree of parallelism of the test measuring procedures, because in certain test devices and systems the number of channels over which the frequency measuring can occur is less than the number of tested semiconductor chips.
Another advantage of the inventive on-chip integrated trimming circuit is that it is also accessible for a self-testing strategy with respect to trimming the oscillator frequency. Note in this regard that the trend in high-density integrated semiconductor chip testing is toward self-testing, which requires only a limited number of external control signals for checking the test run. Unlike in iterative trimming by an external testing device, with the aid of the inventive semiconductor chip which is realized with an integrated trimming circuit and which contains an on-chip trimming circuit for the oscillator frequency, correction addresses do not need to be transferred to the semiconductor chip. This makes possible chip-internal trimming (self-trimming) as an advantageous enhancement for any more far-reaching self-testing strategy in which the interface to the semiconductor chip is reduced to such an extent that a transfer of correction addresses is no longer possible.
Another advantage of the inventive on-chip integrated trimming circuit is that the trimming of the oscillator frequency by the external testing device additionally requires only that one external clock signal be provided, which can be used by a plurality of tested semiconductor chips in a parallel fashion. This requires a single line via a single contact to a test head (i.e. to the external testing device), whereas the conventional approach to external frequency
Beer Peter
Ohlhoff Carsten
Greenberg Laurence A.
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
Tran Andrew Q.
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