Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular power supply distribution means
Reexamination Certificate
1999-08-19
2002-05-21
Flynn, Nathan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular power supply distribution means
C257S208000, C257S700000, C257S203000, C257S691000
Reexamination Certificate
active
06392259
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor chip having circuits which are produced in at least one layer of a semiconductor substrate and disposed in at least one group, and supply and signal lines extending in at least one interconnect plane over the circuits.
Such a semiconductor chip is known from European Patent Application 0 378 306 A2. In that semiconductor chip, a first circuit group is disposed in a secured region and a second circuit group is disposed in a nonsecured region. In the known semiconductor chip, the first region is secured by a conductive layer which is disposed over the interconnect plane of the first circuit group. That conductive layer is electrically connected to the circuit group, and that circuit group is only capable of functioning as intended if the layer is intact.
The first circuit group in that case includes a microprocessor as well as associated peripheral circuits such as memories and a transfer logic circuit. The memories may, in particular, contain secret information. It is also conceivable for the microprocessor to have a special structure which is particularly well-suited to security-relevant functions. Espionage, such as through the use of a scanning electron microscope during the operation of the circuit, is prevented through the use of the conductive layer, the integrity of which is constantly checked.
However, that conductive layer requires a further process step in the production of the semiconductor chip. Furthermore, corresponding evaluation circuits are needed for detecting the integrity of the conductive layer.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor chip with a surface covering, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices of this general type.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor chip, comprising a semiconductor substrate having at least one layer; circuits produced in the at least one layer of the semiconductor substrate, the circuits disposed in at least one group; at least one interconnect plane disposed over the circuits; and supply and signal lines extending in the at least one interconnect plane over at least one group of the circuits, the supply and signal lines having a maximally large width defining a distance between each two of the supply and signal lines, the distance being at most approximately twice a minimum distance achievable according to a relevant state of a technology generation.
In accordance with a concomitant feature of the invention, the distance between two lines essentially corresponds approximately to the minimal distance achievable according to the relevant state of a technology generation.
This essentially means that the distance between lines along the majority of the respective line lengths is the minimum, or at most twice as great as the minimum. By virtue of this small distance, on one hand the chip surface is almost fully covered by the conductive interconnect layer which is required in any case and is protected against optical as well as electron-optical examination. On the other hand, extensive removal of the lines, in order to make it possible to carry out optical surface examination, would have the effect of causing the circuits to no longer function, without further detector circuits having been needed.
A merely point-wise removal of the lines, for example in order to separate circuits parts, would not succeed since welding of neighboring lines would result due to the small distance.
The widening of the lines is carried out during the layout of the topology of the semiconductor chip. In this case, the ground lines are initially configured to be as wide as possible in order to guarantee the best possible capacitive coupling of ground to the substrate, as well as to guarantee a low-impedance voltage supply with minimal coupling of the other signal lines to one another. In the next step, the supply voltage lines are widened. It is not until the end that the signal lines are widened, in order to ensure the least possible coupling of the signal lines to one another.
The widening of the lines according to the invention in at least one interconnect plane is carried out at least over security-critical circuit parts such as memories for secret codes or special encryption circuits. It is, however, advantageous to widen the lines over the entire surface, in order to give a prospective attacker no possible indication of where security-relevant circuit parts are to be found.
If there are several interconnect planes, it is possible to cover different circuit groups in different interconnect planes. It is also possible in this case for the coverings to overlap. Furthermore, in the case of several interconnect planes, it is possible to provide several complete coverings without an extra outlay.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor chip with a surface covering, it Be is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
REFERENCES:
patent: 4434361 (1984-02-01), Meinguss et al.
patent: 4716314 (1987-12-01), Mulder et al.
patent: 0 378 306 (1990-07-01), None
patent: 0 764 985 (1997-03-01), None
International Patent Application WO 96/16445 (Beaumont), dated May 30, 1996.
Allinger Robert
Pockrandt Wolfgang
Flynn Nathan
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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