Semiconductor chip with post-passivation scheme formed over...

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads

Reexamination Certificate

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Details

C257S780000, C257S784000, C257SE23021

Reexamination Certificate

active

07397121

ABSTRACT:
The invention provides a semiconductor chip comprising an interconnecting structure over said passivation layer. The interconnecting structure comprises a first contact pad connected to a second contact pad exposed by an opening in a passivation layer. A metal bump is on the first contact pad and over multiple semiconductor devices, wherein the metal bump has more than 50 percent by weight of gold and has a height of between 8 and 50 microns.

REFERENCES:
patent: 6620728 (2003-09-01), Lin
patent: 6861762 (2005-03-01), Rotem
patent: 2004/0029404 (2004-02-01), Lin
patent: 2004/0166659 (2004-08-01), Lin et al.
patent: 2005/0017343 (2005-01-01), Kwon et al.
patent: 2005/0121804 (2005-06-01), Kuo et al.

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