Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-10-09
2003-12-30
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S535000, C257S723000, C361S306200, C361S306300, C361S311000
Reexamination Certificate
active
06670692
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip and, more particularly, to a semiconductor chip integrated with partially embedded decoupling capacitors for reducing delta-I noise during operations.
2. Description of the Related Art
In a normal configuration of semiconductor chips, power lines and ground lines are routed to logic gates in integrated circuits. External power supply provides current which flows from the power lines, through the logic gates, and finally into the ground lines. During the switching of the logic gates, a large amount of change in the current occurs within a short period of time. The change in the current causes delta-I noise in the voltage of the power and ground lines due to the resistive, capacitive, and possible inductive nature of the semiconductor chip.
This phenomenon becomes more remarkable for semiconductor chips with a high integration density of circuits at a high-speed operation. More specifically, in the field of deep sub-micro processing technology, the power supply voltage is reduced to a lower level, resulting in increasing susceptibility of the semiconductor chips with the high integration density of circuits to the delta-I noise. In this case, the delta-I noise has a direct, adverse effect on the maximum operating frequency of the semiconductor chips.
FIG. 1
is a top view showing a normal semiconductor chip mounted on a lead frame. As shown in
FIG. 1
, a semiconductor chip
10
is provided with a plurality of bonding pads
11
thereon. The bonding pads
11
are formed on a passivation layer
12
, which is the topmost layer of the semiconductor chip
10
, and connected with underlying, corresponding embedded metal layers (not shown) of the semiconductor chip
10
through via holes opened on the passivation layer
12
. Each of the bonding pads
11
is connected to a corresponding terminal
13
of a lead frame
14
through a bonding wire
15
.
FIG. 2
is a circuit diagram showing an equivalent circuit of FIG.
1
. As shown in
FIG. 2
, symbol V
s
represents an external DC voltage supply on a motherboard (not shown) for supporting the lead frame
14
. Symbols R
t
and L
p
represent an equivalent resistance and inductance between the external DC voltage supply V
s
and the lead frame
14
, respectively. Each of symbols C
p1
and C
p2
represent a mid-frequency decoupling capacitor. Regarding to the bonding wires
15
, each of them has an equivalent resistance R
w
and inductance L
w
as well as an equivalent resistance R
c
in connection with two adjacent bonding wires
15
. Regarding to the semiconductor chip
10
, symbol I
p
represents the current flowing in the semiconductor chip
10
from power lines VDD to ground lines VSS while symbol C
comp
represents a built-in high-frequency decoupling capacitor.
As clearly seen from
FIG. 2
, the bonding wires
15
have equivalent inductances L
w
, which causes the delta-I noise during the switching of the logic gates formed inside the semiconductor chip
15
. More specifically, when the logic gates switch, the change in current
(
referred
to
as
ⅆ
i
ⅆ
t
)
develops a voltage (referred to as &Dgr;v) expressed by the following equation:
Δ
v
=
L
w
ⅆ
i
ⅆ
t
Such instability of voltage caused by the delta-I noise deteriorates the quality of power supply delivering to the semiconductor chip
10
and thus suppresses the possibility of high-speed operations.
As a countermeasure against the delta-I noise, decoupling capacitors have been suggested to be inserted between the semiconductor chip
10
and the bonding wires
15
.
FIG. 3
is a top view showing a semiconductor chip with conventional decoupling capacitors. As shown in
FIG. 3
, two multi-layer ceramic capacitors (MLCCs)
16
are used as the decoupling capacitors, for example. Each of the MLCCs
16
is connected in series between the power pad and ground pad of the semiconductor chip
15
. The equivalent circuit of each of the MLCCs
16
includes a resistance R
g
, an inductance L
g
, and a capacitance C
g
, connecting in series with each other, as shown in FIG.
4
. Although the addition of the MLCCs
16
reduces the delta-I noise well, there are at least two shortcomings regarding to the use of the MLCCs
16
. First, it is necessary to bond the MLCCs
16
onto the pads of the semiconductor chip
10
. Such bonding of the MLCCs does not only increase overall processing steps but also deteriorates the reliability of the semiconductor chip
10
. Besides, the delta-I noise reducing efficiency of the MLCCs
16
is inevitably restrained by the equivalent inductance L
g
thereof.
To avoid these shortcomings, a conventional metal-insulator-metal (MIM) process is employed to form another type of decoupling capacitor. Typically, the semiconductor chip with a high integration density of circuits includes a plurality of embedded metal layers separated by insulator layers. Two of these metal layers, e.g., an n
th
metal layer and (n−1)
th
metal layer in an n-metal-layer chip structure, are used as power and ground metal layers, respectively. According to the MIM process, an additional metal layer is embedded in one insulator layer between the power and ground metal layers to work together with the ground metal layer as a decoupling capacitor.
FIG. 5
is a circuit diagram showing an equivalent circuit of a semiconductor chip with an MIM decoupling capacitor
17
. Although the use of the MIM decoupling capacitor
17
has an advantage of eliminating the equivalent inductance compared with the use of the MLCC, the manufacturing process of the semiconductor chip becomes more complicated due to the formation of the MIM decoupling capacitor
17
.
SUMMARY OF THE INVENTION
In view of the above-mentioned problems, an object of the present invention is to provide a semiconductor chip capable of reducing the delta-I noise by means of a decoupling capacitor without equivalent inductance.
Another object of the present invention is to provide a semiconductor chip capable of reducing the delta-I noise by means of a decoupling capacitor being fabricated without changing the original circuit layout and manufacturing process of the semiconductor chip.
Still another object of the present invention is to provide a semiconductor chip capable of reducing the delta-I noise by means of a decoupling capacitor being fabricated at low cost and high reliability.
According to the present invention, a partially embedded decoupling capacitor is provided as an integral part of a semiconductor chip for reducing the delta-I noise. The semiconductor chip includes a plurality of embedded metal layers, a passivation layer formed above the plurality of embedded metal layers as a topmost layer of the semiconductor chip, and a plurality of bonding pads disposed on the passivation layer. A surface planar metal pattern is formed on the passivation layer and electrically connected to one of the plurality of embedded metal layers through one of the plurality of bonding pads or a via hole opened on the passivation layer at a location separated from the plurality of bonding pads. For example, the surface planar metal pattern may be connected to a power layer or a ground layer of the semiconductor chip.
Therefore, a partially embedded decoupling capacitor is made up of the surface planar metal pattern as an electrode, others of the plurality of embedded metal layers as opposite electrodes, and the passivation layer sandwiched therebetween as a dielectric layer. Since connected to one of the plurality of embedded metal layers, the surface planar metal pattern further serves as a heat sink for dissipating heat directly from the inside of the semiconductor chip.
The partially embedded decoupling capacitor according to the present invention is easy to fabricate without changing the original circuit layout and manufacturing process of the semiconductor chip. As a result, the production cost is reduced and the reliability of the decoup
Hsu Tsung-chi
Lin Wei-feng
Lu Ming-huan
Shih Ching-chang
Tu Chun-An
Flynn Nathan J.
Greene Pershelle
Martine & Penilla LLP
Silicon Integrated Systems Corp.
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