Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2008-07-01
2008-07-01
Lebentritt, Michael S. (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S600000, C438S622000, C257SE21595
Reexamination Certificate
active
11127782
ABSTRACT:
A metallization surface (5), which acts as an etching stop layer during the production of openings (4) in a passivation layer (3) applied to its upper face and protects an interconnect structure (6) arranged underneath it, is arranged in an uppermost metallization level (1). A further opening is produced in the metal surface (5), through which a focused ion beam is aimed at the interconnect structure (6) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.
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Gerstmeier Günter
Huber Andreas
Sommer Michael Bernhard
Infineon - Technologies AG
Isaac Stanetta D
Lebentritt Michael S.
Slater & Matsil L.L.P.
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