Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2002-03-13
2003-11-18
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000
Reexamination Certificate
active
06649428
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor chips laminated on a substrate, a semiconductor integrated circuit device using the same, and a method of selecting a semiconductor chip.
2. Description of the Related Art
In recent years, semiconductor integrated circuits have been realized in a highly integrated form and in an SOC (system-on-chip) form. In particular, semiconductor integrated circuits have been fabricated in a multi-chip form by laminating a plurality of semiconductor chips one upon the other relying upon a chip-mounting technology. The chip-mounting method for realizing the multi-chip devices can be represented by a super-connect technology by which a plurality of electrode terminals are arranged on the surfaces of semiconductor chips, and the semiconductor chips are laminated one upon the other and are connected together through electrode terminals. Study has been forwarded to put the super-connect technology into practical use, and has been expected as technology of the next generation. For example, a plurality of semiconductor chips forming a memory circuit are laminated one upon the other relying upon the super-connect technology in order to obtain a memory of a high density and of a large storage capacity.
In general, the memory of a large storage capacity formed by using the super-connect technology has a structure in which the semiconductor chips are laminated one upon the other via bumps to form a plurality of layers, the semiconductor chips having the same wiring pattern including electrode terminals and circuit elements. When the semiconductor chips are laminated to form the plurality of layers, signals are needed for selecting a chip which is in operation to write or read the data. When the semiconductor chips that are laminated all have the same wiring pattern, however, the positions of the electrode terminals for receiving chip selection signals become all in agreement, permitting the same chip selection signal to enter into every semiconductor chip, which makes it difficult to select the chip that is in operation.
This problem can be avoided by the following two methods. According to a first method, a plurality of semiconductor chips are prepared by using a plurality of exposure masks having different circuit patterns in a step of photolithography while deviating the electrode terminals that receive the chip selection signals. These semiconductor chips are, then, laminated on a substrate via bumps, and selection signals are successively output from the substrate to the electrode terminals that receive chip selection signals of the semiconductor chips, thereby to select the chip which is in operation.
According to a second method, a plurality of semiconductor chips are prepared by forming the same wiring pattern, irradiating a portion of the wiring pattern of each of the semiconductor chips with a laser beam to form electrode terminals which are, respectively, deviated to receive chip selection signals. These semiconductor chips are laminated on the substrate via bumps, and selection signals are successively output from the substrate to the electrode terminals that receive chip selection signals of the semiconductor chips, thereby to select the chip which is in operation.
However, the first method requires a plurality of circuit designs as well as a plurality of pieces of expensive masks for exposure. Besides, an increased number of photolithography steps are required. The second method requires a step of cutting the wiring pattern by the irradiation with a laser beam. Thus, either method requires an increased number of manufacturing steps driving up the cost of production.
SUMMARY OF THE INVENTION
It is an object of this invention to provide semiconductor chips which enable a predetermined chip to be selected by chip selection signals from an external unit despite the chips are laminated in a plural number having the same wiring pattern, to provide a semiconductor integrated circuit device using the such chips and to provide a method of selecting a semiconductor chip.
The above object is accomplished by a semiconductor chip comprising a plurality of first electrode terminals arranged on a front surface maintaining a predetermined pitch to receive reference signals for producing comparison signals that are to be compared with chip selection signals in a comparator circuit to select a chip, a plurality of second electrode terminals arranged on a back surface opposed to the front surface each being deviated by one pitch from the plurality of the first electrode terminals to output the reference signals input to the first electrode terminals, and connection portions for electrically connecting the first and second electrode terminals that are deviated by one pitch.
REFERENCES:
patent: 4910582 (1990-03-01), Miyamoto et al.
patent: 5637187 (1997-06-01), Takasu et al.
patent: RE35807 (1998-05-01), Iversen et al.
patent: 6094370 (2000-07-01), Takashima
patent: 5-129463 (1993-05-01), None
patent: 2001-24151 (2001-01-01), None
Armstrong Westerman & Hattori, LLP.
Fujitsu Limited
Luk Olivia T
Niebling John F.
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