Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2001-09-07
2003-09-09
Graybill, David E (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S778000, C257S779000, C257S786000, C438S108000, C438S109000, C438S599000, C438S612000, C438S620000, C438S669000
Reexamination Certificate
active
06617694
ABSTRACT:
Japanese Patent Application No. 2000-273030 filed Sep. 8, 2000 and Japanese Patent Application No. 2001-268333 filed Sep. 5, 2001 are hereby incorporated by reference in its entirety.
TECHNICAL FIELD
The present invention relates to a semiconductor chip, a semiconductor device, methods of fabricating thereof, a circuit board and an electronic device.
BACKGROUND
Stacked type semiconductor devices have been developed so far. For example, the structure that has two semiconductor chips adhered back to back or the structure that has two semiconductor chips mounted face down on both sides of a substrate are known. In this case, if the positions of the pads of the two semiconductor chips have a plane symmetry relationship, it is easy to take electric connection. This led to the use of two chips whose pad positions have a plane symmetry relationship, i.e., mirror chips. According to the conventional mirror chips, however, the internal circuits in the two chips also had a plane symmetry relationship. It was therefore necessary to fabricate two chips with different masks.
SUMMARY
A semiconductor device according to one aspect of the present invention comprises:
a first semiconductor chip comprising a plurality of first terminals, a plurality of first buffer circuits for at least one of inputting and outputting, a plurality of first interconnecting lines which electrically connect the plurality of first terminals to the plurality of first buffer circuits, and a first internal circuit electrically connected to the plurality of first buffer circuits; and
a second semiconductor chip comprising a plurality of second terminals, a plurality of second buffer circuits for at least one of inputting and outputting, a plurality of second interconnecting lines which electrically connect the plurality of second terminals to the plurality of second buffer circuits, and a second internal circuit electrically connected to the plurality of second buffer circuits,
wherein positions of the plurality of first terminals and positions of the plurality of second terminals are in plane symmetry,
wherein the first internal circuit is identical with the second internal circuit at least in design, and
wherein at least a part of the plurality of first interconnecting lines and at least a part of the plurality of second interconnecting lines are formed in different patterns.
A semiconductor chip according to another aspect of the present invention comprises:
a plurality of terminals;
a plurality of buffer circuits for at least one of inputting and outputting;
a plurality of interconnecting lines which electrically connect the plurality of terminals to the plurality of buffer circuits; and
an internal circuit electrically connected to the plurality of buffer circuits,
wherein one terminal T
1
in the plurality of terminals corresponds to two circuits C
1
and C
2
in the plurality of buffer circuits, and
wherein the terminal T
1
is selectively connected to the circuit C
1
by a part of the plurality of interconnecting lines.
A semiconductor chip according to further aspect of the present invention comprises:
a plurality of terminals;
a plurality of buffer circuits for at least one of inputting and outputting;
a plurality of interconnecting lines which electrically connect the plurality of terminals to the plurality of buffer circuits; and
an internal circuit electrically connected to the plurality of buffer circuits,
wherein each of the plurality of terminals is connected to any one of the plurality of buffer circuits by a part of the plurality of interconnecting lines, and
wherein the plurality of buffer circuits are arranged in a line at a central portion of the semiconductor chip.
A semiconductor device according to still another aspect of the present invention comprises a plurality of stacked semiconductor chips,
wherein each of the semiconductor chips is the above described semiconductor chip.
A semiconductor device according to still further aspect of the present invention comprises a plurality of stacked semiconductor chips,
wherein at least one of the semiconductor chips is the above described semiconductor chip.
A circuit board according to still further aspect of the present invention has the above described semiconductor device mounted thereon.
An electronic device according to still further aspect of the present invention comprises the above described semiconductor device.
A method of fabricating a semiconductor chip according to still further aspect of the present invention comprises forming a plurality of terminals, a plurality of buffer circuits for at least one of inputting and outputting, a plurality of interconnecting lines which electrically connect the plurality of terminals to the plurality of buffer circuits, and an internal circuit electrically connected to the plurality of buffer circuits,
wherein one terminal T
1
in the plurality of terminals corresponds to the two circuits C
1
and C
2
in the plurality of buffer circuits, and
wherein the terminal T
1
is selectively connected to the circuit C
1
by a part of the plurality of interconnecting lines.
A method of fabricating a semiconductor chip according to yet another aspect of the present invention comprises forming a plurality of terminals, a plurality of buffer circuits for at least one of inputting and outputting, a plurality of interconnecting lines which electrically connect the plurality of terminals to the plurality of buffer circuits, and an internal circuit electrically connected to the plurality of buffer circuits,
wherein each of the plurality of terminals is connected to any one of the plurality of buffer circuits by a part of the plurality of interconnecting lines, and
wherein the plurality of buffer circuits are arranged in a line at a central portion of the semiconductor chip.
A method of fabricating a semiconductor device according to yet further aspect of the present invention comprises:
fabricating a first semiconductor chip comprising a plurality of first terminals, a plurality of first buffer circuits for at least one of inputting and outputting, a plurality of first interconnecting lines which electrically connect the plurality of first terminals to the plurality of first buffer circuits, and a first internal circuit electrically connected to the plurality of first buffer circuits, and
fabricating a second semiconductor chip comprising a plurality of second terminals, a plurality of second buffer circuits for at least one of inputting and outputting, second interconnecting lines which electrically connect the plurality of second terminals to the plurality of second buffer circuits, and a second internal circuit electrically connected to the plurality of second buffer circuits;
wherein the first and second internal circuits are formed at least with a same mask in design in such a way as to have a same structure in design;
wherein the plurality of first terminals and the plurality of second terminals are formed at least with a same mask in design in such a way as to be arranged symmetrically with respect to a line in a same arrangement in design; and
wherein at least a part of the plurality of first interconnecting lines and at least a part of the plurality of second interconnecting lines are formed with masks of different designs.
REFERENCES:
patent: 6326681 (2001-12-01), Murakami et al.
patent: 6426560 (2002-07-01), Kawamura et al.
Kodaira Satoru
Kumagai Takashi
Tomohiro Yasuhiko
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