Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2003-02-03
2004-11-16
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
C365S051000, C365S189030, C365S195000, C365S226000
Reexamination Certificate
active
06819580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip that has a plurality of pins serving as signal input/output terminals.
2. Description of the Background Art
FIG. 9
is a diagram showing the structure of a common semiconductor chip that includes logic circuitry, memory circuitry, etc. This semiconductor chip CP includes core circuitry CR that provides logical and memory functions for processing and storing signals and an input/output controller IOC for coordinating the input/output of the signals. The semiconductor chip CP is also provided with a large number of pins PN located along its periphery and serving as signal input/output terminals.
The input/output controller IOC includes an input/output buffer BF and a setting memory STM. The input/output buffer BF times and coordinates the transfer of signals between the core circuitry CR and the pins PN, i.e. an input signal Din to the core circuitry CR and an output signal Dout from the core circuitry CR. The setting memory STM, formed of a register, is a storage area for storing settings for the control of input/output signals by the input/output buffer BF.
Now, when a semiconductor chip is encapsulated, e.g. with resin, and packaged, all pins on the semiconductor chip may or may not be connected to external lead terminals of the package.
FIG. 10
is a diagram that shows a simple example of the packaging of a semiconductor chip, where a semiconductor chip CPa has eight pins that are all connected to the external lead terminals of the package. On the other hand,
FIG. 11
shows an example in which some of the pins of the same semiconductor chip CPa are not connected to external lead terminals of the package.
In
FIG. 10
, pins PN
1
to PN
8
on the semiconductor chip CPa are respectively connected to external lead terminals LD
1
to LD
8
of the package PKa through bonding wires WB
1
to WB
8
.
On the other hand, in
FIG. 11
, the pins PN
1
to PN
3
and PN
6
to PN
8
on the semiconductor chip CPa are respectively connected to the external lead terminals LD
1
to LD
3
and LD
6
to LD
8
of the package PKb through bonding wires WB
1
to WB
3
and WB
6
to WB
8
, but the package PKb does not have bonding wires and external lead terminals for the fourth pin PN
4
and the fifth pin PN
5
. That is to say, the fourth pin PN
4
and the fifth pin PN
5
are dead (unconnected) pins that are not used.
In general, a semiconductor chip CPa often has such dead pins, depending on its use. For example, when specifications drawn up by one customer need the fourth and fifth pins PN
4
and PN
5
but specifications by another customer do not need the fourth and fifth pins PN
4
and PN
5
, it is a common practice to deliver the same semiconductor chips CPa enclosed in the package PKa of FIG.
10
and the package PKb of
FIG. 11
respectively to the two customers. The package PKb of
FIG. 1
, which has no unnecessary external lead terminals, can be smaller in size than the package PKa of FIG.
10
.
Now, the input/output buffer BF sets the directions of signals at individual pins on the basis of the contents stored in the setting memory STM, so as to determine whether the individual pins on the semiconductor chip serve as input pins for receiving input signals from the outside or as output pins for extracting output signals to the outside. The input/output buffer BF has a mechanism, for each pin, to set the signal direction.
FIG. 12
is a diagram showing an example of the signal direction setting mechanism in a conventional input/output buffer BFe, where, among the pins PN
1
to PN
8
on the semiconductor chip CPa, the fourth pin PN
4
and the fifth pin PN
5
are shown with their respective mechanisms.
For example, the signal direction setting mechanism for the fourth pin PN
4
includes a 3-state buffer TB
4
and a transfer gate TG
4
.
The 3-state buffer TB
4
receives an output signal Dout from the core circuitry CR at its input end, and its output end is connected to the fourth pin PN
4
. Also, information stored in the setting memory STMe is given as a signal SG
4
c
, e.g. logically inverted, to the enable end of the 3-state buffer TB
4
.
The input end of the transfer gate TG
4
is connected to the fourth pin PN
4
and its output end outputs an input signal Din to the core circuitry CR. The signal SG
4
c
is given to the gate of the N-channel MOS transistor of the transfer gate TG
4
, and also to the gate of the P-channel MOS transistor of the transfer gate TG
4
through an inverter IV
4
.
The signal SG
4
c
is applied to both of the 3-state buffer TB
4
and the transfer gate TG
4
as shown above, and then it can be determined whether to make the fourth pin PN
4
function as an input pin or an output pin, depending on whether the signal SG
4
c
is High or Low. That is to say, the fourth pin PN
4
functions as an input pin when the signal SG
4
c
is High, and it functions as an output pin when the signal SG
4
c
is Low.
A similar signal direction setting mechanism is provided also for the fifth pin PN
5
, where information stored in the setting memory STMe is given as a signal SG
5
c
to both of a 3-state buffer TB
5
and a transfer gate TG
5
. While
FIG. 12
only shows signal direction setting mechanisms associated with the pins PN
4
and PN
5
, it is understood that similar mechanisms (not shown) are provided also for other pins PN
1
to PN
3
, PN
6
to PN
8
.
FIG. 13
is a diagram illustrating the contents stored in a memory table MTe contained in the setting memory STMe. The memory table MTe stores data about signal input/output directions at the pins PN
1
to PN
8
, as well as other information (not shown) such as control data for an input/output control register (not shown) provided in the semiconductor chip CPa. Such memory table MTe is called SFR (Special Function Register), for example.
For instance, the data ST
4
about the signal direction at the fourth pin PN
4
includes bit data Sin
4
in which a flag is set ON when the fourth pin PN
4
should function as an input pin and bit data Sout
4
in which a flag is set ON when the fourth pin PN
4
should function as an output pin. Similarly, the data ST
5
about the signal direction at the fifth pin PN
5
includes bit data Sin
5
and Sout
5
.
It is then determined, depending on the states of the flags in the bit data Sin
4
and Sout
4
, whether the signal SG
4
c
given to the 3-state buffer TB
4
and the transfer gate TG
4
associated with the fourth pin PN
4
should be High or Low. That is to say, when the flag in the bit data Sin
4
is ON and the flag in the bit data Sout
4
is OFF, then the signal SG
4
c
is High and the fourth pin PN
4
functions as an input pin. On the other hand, when the flag in the bit data Sin
4
is OFF and the flag in the bit data Sout
4
is ON, then the signal SG
4
c
is Low and the fourth pin PN
4
functions as an output pin.
The same applies to the signal SG
5
c
for the fifth pin PN
5
, and also to other pins PN
1
to PN
3
and PN
6
to PN
8
.
Such signal direction setting mechanisms can thus specify whether to make the individual pins PN
1
to PN
8
serve as input pins or output pins.
When a pin is dead (not connected) and functions as an input pin, then the potential at the dead pin comes in a floating state, so that the signal level, High or Low, cannot be determined. This may cause malfunctions of the core circuitry CR.
Accordingly, in the memory table MTe of
FIG. 13
, the flags in the bit data Sin
4
and Sout
4
must be properly set so that the dead pin functions as an output pin. That is, when the dead pin functions as an output pin, then the potential is fixed at the potential of a signal generated in the core circuitry CR (either High or Low). Such potential control for dead pins is generally referred to as “dead pin potential control process.”
However, the setting of data in the memory table MTe for specifying the input/output directions of signals at the individual pins PN
1
to PN
8
is done by the customer to which the semiconductor chip CPa has been delivered. When the fourth pin PN
4
an
Konishi Masayuki
Shimomura Takehiko
Renesas Technology Corp.
Tran Andrew Q.
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