Semiconductor chip scale package and method of producing such

Details Semiconductor chip scale package and method of producing such Semiconductor chip scale package and method of producing such

1996-12-23

1999-06-22

Graybill, David

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Including adhesive bonding step

438121, 438125, 438614, 257673, 257690, 257737, 257783, H01L 2158, H01L 2160

Patent

active

059151692

ABSTRACT:
A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.

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patent: 5461197 (1995-10-01), Hiruta et al.
patent: 5640051 (1997-06-01), Tomura et al.

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