Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1996-03-28
2002-12-24
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S203000, C257S786000, C257S734000
Reexamination Certificate
active
06498396
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor packages of CSP (Chip Scale Package) and BGA (Ball Grid Array) structures of a high chip occupying rate and improved in packaging density, and more particularly, to a semiconductor package of a CSP structure and a BGA structure in which reliability as a semiconductor device is prevented from being degraded.
2. Description of the Background Art
A semiconductor package of a CSP structure has been developed as one that can have a high chip occupying rate (more than 90%) and that can have packaging density improved drastically. Such a package is released in, for example, ISSCC (International Solid-State Circuits Conference) 94.
As shown in
FIG. 30
, a semiconductor package of a CSP structure (referred to as CSP hereinafter) includes a semiconductor chip
1
, a connection interconnection
3
, a bump electrode
4
, and a mold resin
5
. Semiconductor chip
1
includes an integrated semiconductor device, and a bonding pad (referred simply as “pad” hereinafter)
2
electrically connected to the integrated semiconductor device. Pad
2
is connected to bump electrode
4
via interconnection
3
formed by photolithography. Mold resin
5
covers the entirety thereof except for the head of bump electrode
4
. This semiconductor package of a CSP structure is mounted on a predetermined board by fusing bump electrode
4
.
Since connection interconnection
3
and bump electrode
4
are formed on semiconductor chip
1
in a CSP, lead pins and wires connecting a lead pin and a pad of a semiconductor chip required in conventional packages do not have to be provided. This eliminates the need of a thick mold that was required to cover the lead pins and wires. Therefore, the thickness of the mold can be reduced significantly. In effect, a CSP allows a package of substantially the same size of a semiconductor chip.
Since interconnection
3
is formed by photolithography, the length and path configuration of connection interconnection
3
can be set arbitrarily. Connection between bump electrode
4
and pad
2
can be implemented easily even when bump electrode
4
and pad
2
are formed at arbitrary positions. Furthermore, wire inductance and input capacitance can be increased to improve electric characteristics by forming interconnecting
3
so that the length between bump electrode
4
and pad
2
is reduced.
FIG. 31
shows a CSP in which connection interconnection
3
is provided with pad
2
arranged at an arbitrary position. As shown in
FIG. 31
, respective pads
2
are formed at arbitrary positions connected to corresponding bump electrodes
4
by connection interconnection
3
formed vertically and horizontally by photolithography.
As shown in
FIG. 31
, a CSP can have pad
2
, connection interconnection
3
and bump electrode
4
formed on arbitrary positions on a semiconductor chip
1
. In forming bump electrode
4
and in mounting the CSP on a board, stress is exerted onto the semiconductor element provided under bump electrode
4
. It was therefore necessary to take care that the stress generated in forming bump electrode
4
and in mounting CSP on a board is as low as possible.
The advantage of forming pad
2
or the like at an arbitrary position on semiconductor chip
1
in the CSP was used just for connecting pad
2
with bump electrode
4
by connection interconnection
3
as shown in
FIGS. 30 and 31
.
In a semiconductor memory such as a DRAM (Dynamic Random Access Memory), the chip area is increased as the capacity thereof becomes greater. However, the demand for increase in speed and reduction in consumption power is insatiable. Increase in the length of the wiring path on a chip due to a larger chip area results in a greater delay in signal transmission to prevent high speed operation.
Furthermore, there is a greater demand for a x16/x32/x64 configuration than a x1/x4/x8 configuration as to the number of data input/output pins corresponding to a multi-bit structure requirement. Increase in the number of bits will require a greater number of output buffers and bonding pads, which in turn will result in a larger chip area. Also, the problem of a power supply noise becomes noticeable.
Furthermore, there is a trend towards a system chip incorporating both memory and logic. Corresponding packaging technology is therefore required.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor package having a bump electrode arranged taking into consideration stress exerted on an underlying semiconductor element so as to prevent reduction in reliability as a semiconductor device.
Another object of the present invention is to provide a semiconductor package effectively taking advantage of the feature of a CSP.
A further object of the present invention is to provide a semiconductor package that can maintain high speed operation even in a semiconductor memory of a great capacity.
Still another object of the present invention is to provide a semiconductor package that can have increase in chip area and power supply noise suppressed even when the number of bits is increased.
A semiconductor package of the present invention includes features set forth in the following on the postulation that it is a semiconductor package including a plurality of external interconnection units formed of a bump electrode for connection with the outside world, on a main surface of a semiconductor chip having an integrated semiconductor device, a pad formed at the semiconductor chip for connection with the integrated semiconductor device, and a connection interconnection formed on the main surface of the semiconductor chip by photolithography for electrically connecting a pad and a bump electrode.
When an integrated semiconductor device includes a fragile circuit that is easily altered in circuit characteristics by an external factor such as mechanical stress, a semiconductor package according to an aspect of the present invention has a bump electrode formed at a region other than the upper portion of the region where the fragile circuit is provided.
Due to this arrangement, mechanical stress is prevented from being exerted on the fragile circuit via the bump electrode in the semiconductor package of the present aspect.
Preferably, the fragile circuit is a sense amplifier circuit formed of a pair of transistors for sensing and amplifying a small potential difference between a pair of bit lines.
By a virtue of the fragile circuit being a transistor circuit, imbalance in the operation characteristics of the transistor pair due to mechanical stress being exerted via the bump electrode is prevented. Therefore, reduction in the sense operation of the sense amplifier circuit can be prevented.
Preferably, the fragile circuit is an analog circuit operating at a small current.
By virtue of the fragile circuit being an analog circuit, deterioration of the operation of the analog circuit due to mechanical stress being exerted via the bump electrode is prevented.
A semiconductor package according to another aspect of the present invention includes at least one power supply pad, and a power supply interconnection. The power supply pad is provided on a main surface of the semiconductor chip to supply power to an integrated semiconductor device. The power supply interconnection is connected to the power supply pad and is provided so as to surround at least a portion of each of the plurality of external interconnection units.
By virtue of the above-described arrangement, an external interconnection unit surrounded by a power supply interconnection is electrically shielded to be immune from another external internal connection unit and to prevent electrical influence to another external interconnection unit.
Preferably, the power supply interconnection surrounding at least a portion of each of the plurality of external interconnection units is formed in a mesh-like manner connected to each other. A plurality of power supply pads are provided with respect to the mesh-like power supply interconnection so
Graybill David E.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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