Semiconductor chip packaging system and a semiconductor chip...

Details Semiconductor chip packaging system and a semiconductor chip... Semiconductor chip packaging system and a semiconductor chip...

2000-08-02

2002-05-21

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

With means to shield device contained in housing or package...

C257S676000

Reexamination Certificate

active

06392286

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a system for packaging a semiconductor chip as a ball grid array (BGA) type or a fine pitch ball grid array (FBGA) type. More particularly, the semiconductor chip packaging system provides an improved cleaning technology of a printed circuit board (PCB) on which the semiconductor chips are mounted and allows in-line arrangement of cleaning equipment and fabricating equipment. Through the in-line arrangement, PCBs can be introduced into the fabricating equipment immediately after finished in the cleaning equipment, whereby the cleaned state of the PCBs can be maintained longer. Furthermore, the present invention relates to a semiconductor chip packaging method using the semiconductor chip packaging system.
2. Description of the Related Art
As the memory capacities of electronic and information devices are enlarged, semiconductor chips such as DRAM and SRAM have trended highly integrated. Accordingly, the sizes of the semiconductor chips are also enlarged. Contrary to the trend of the large semiconductor chips, packaging technologies take a trend of making semiconductor chip package lighter, thinner, simpler and smaller depending on the miniaturization and lightness of the electronic and information devices.
Recently, with rapid developments of semiconductor chip packaging technology, surface mounted semiconductor packages such as BGA semiconductor packages which are capable of accommodating far larger semiconductor chips and have a size reduced to a minimum have been developed. With repetition of developments in the technology, the sizes of semiconductor packages, e.g., a chip scale semiconductor package such as a FBGA semiconductor package, are close to 120% of the size of a semiconductor chip.
Such conventional BGA semiconductor package structures are disclosed in detail in U.S. Pat. No. 5,663,593 entitled “Ball grid array package with lead frame”, U.S. Pat. No. 5,706,178 entitled “Ball grid array integrated circuit package that has vias located within the solder pads of a package”, U.S. Pat. No. 5,708,567 entitled “Ball grid array semiconductor package with ring-type heat sink”, U.S. Pat. No. 5,720,050 entitled “Semiconductor package substrate and ball grid array semiconductor package using same”, U.S. Pat. No. 5,741,729 entitled “Ball grid array package for an integrated circuit”, U.S. Pat. No. 5,748,450 entitled “BGA package using a dummy ball and a repairing method thereof”, U.S. Pat. No. 5,796,170 entitled “Ball grid array integrated circuit packages” and so on.
Generally, the conventional semiconductor packages such as a duel inline package (DIP) type semiconductor package and a small outline J-leaded package (SOJ) type semiconductor package make an electrical connection between semiconductor chips and external devices using lead frames. On the other hand, the BGA semiconductor packages and the FBGA semiconductor packages use a substantially different member, e.g., a PCB, instead of the lead frame.
Generally, the PCBs used in the BGA and FBGA semiconductor packages are coated with photo solder resist (PSR).
However, there are several serious problems in using the BGA and FBGA semiconductor packages in the fabrication line, The problems will be described hereinafter.
As described above, the BGA and FBGA semiconductor packages make electrical connection between semiconductor chips and external devices using a PCB that is substantially different from the lead frame.
However, since, differently from the conventional lead frame, the PCB has a structure that is coated with PSR on the surface thereof, the PCB absorbs moisture too soon and is easily transformed. Moreover, the PCB is easily contaminated by outer contamination sources.
In the case that the semiconductor chips are mounted on the PCB under the condition that the PCB suffers from the above-described problems, a finally completed BGA or FBGA semiconductor package may have problems in that semiconductor chips are separated from the PCB, wires are separated from leads of the PCB, or molded objects may be separated from the PCB. These problems result in the degeneration in performance of electronic devices with the semiconductor packages.
In order to prevent the above described problems, plasma cleaning processes are performed to remove both of the moisture within the PCB and contamination materials on the surface of the PCB at mid time of the whole semiconductor assembly process, e.g., before die attaching process, before wire bonding process and before molding process.
In this case, the PCB is introduced into a chamber filled with a plasma gas before a subsequent process is performed. The PCB is then exposed to the plasma gas such that the contamination materials on the PCB reacts on the plasma gas. As a result, the moisture within the PCB and the contamination materials attached to the surface of the PCB are removed.
For example, right before die attaching process is performed, an operator manually introduces the PCB into the plasma chamber. After the plasma cleaning process is completed, the operator manually takes out the PCB from the chamber. This process is repeatedly performed. PCBs unloaded from the chambers through the aforementioned process, are collected in a lot number and the operator loads the collected PCBs to die attaching equipment at a time so that the die attaching process can be rapidly performed.
Usually, the plasma cleaning effects lasts 4 to 6 hours. Accordingly, special attention should be payed on loading the PCBs to another process within 4 to 6 hours since the plasma cleaning process has been completed in the conventional fabrication line.
Usually, the plasma cleaning effects last 4 to 6 hours. Accordingly, special attention should be paid on loading the PCBs to another process within 4 to 6 hours since the plasma cleaning process has been completed in the conventional fabrication line.
This is because the PCBs are not loaded to the subsequent assembly process according to the processed order of the PCBs immediately after the cleaning process but the PCBs are held in an air environment outside the assembly equipment until the PCBs are completely collected from the plurality of chambers.
Thus, initially collected PCBs are held for a long time outside the assembly equipment until remaining PCBs are collected. Finally, a great amount of time difference, e.g., more than 6 hours, occurs between the cleaning step and the substantial assembly process.
In the event that the PCBs are loaded to the assembly process after more than 6 hours when the cleaning effect is completely disappeared, PCBs still suffer from the moisture and contamination problems.
Moreover, since a large part of the PCB cleaning process is manually performed by an operator, standby time of the PCB is increased.
In order to prevent such problems in advance, the PCBs should be introduced into the assembly process immediately after the cleaning process. However, the immediate introduction of the cleaned PCBs requires an extra operator in charge of the job. This results in reduced production efficiency.
In the meanwhile, if in-line arrangement of the plasma cleaning chamber and the assembly equipment is realized, these problems can be solved. However, the chamber should be airtight and the inside of the chamber should be under high vacuum condition for the plasma process. Accordingly, in-line arrangement of the cleaning chamber and the fabricating equipment is actually impossible.
Therefore, though the problems of the prior art are thoroughly understood, clean solution cannot be found in the prior art.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to load a PCB into the assembly equipment immediately after the cleaning step of the PCB has been completed by improving PCB cleaning technology and thereby to arrange the cleaning equipment and the fabricating equipment in-line.
It is another object of the present invention to maintain the cleaned state of the PCB longer by reducing the time difference between the cleaning s

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