Semiconductor chip packaging structure including a ground plane

Details Semiconductor chip packaging structure including a ground plane Semiconductor chip packaging structure including a ground plane

1993-03-04

1995-03-21

James, Andrew J.

Active solid-state devices (e.g., transistors, solid-state diode

With shielding

257758, 257774, 257508, 257691, 174 35R, 361816, H01L 4900, H01L 2348, H01L 2704, H01L 2944

Patent

active

053999029

ABSTRACT:
A semiconductor chip package wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that has a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.

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H. R. Bickford et al. "Dual Metal Thickness Tape Automated Bonding Leadframe", IBM Tech Discl. Bull, vol. 32, No. 3A, Aug. 1989, p. 85.

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