Semiconductor chip packages having reduced stress

Details Semiconductor chip packages having reduced stress Semiconductor chip packages having reduced stress

2007-10-12

2010-11-30

Landau, Matthew C (Department: 2813)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Metallic housing or support

C438S125000, C257S680000, C257S693000, C257S701000, C257S729000, C257SE23023, C257SE23194, C257SE23060, C257SE23181, C257SE23191, C257SE23193, C257SE21500, C257SE21511

Reexamination Certificate

active

07842552

ABSTRACT:
A structure and a method for forming the same. The structure includes (i) a carrier substrate which includes substrate pads, (ii) a chip physically attached to the carrier substrate, and (iii) a first frame physically attached to the carrier substrate. A CTE (coefficient of thermal expansion) of the first frame is substantially lower than a CTE of the carrier substrate.

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patent: 6502926 (2003-01-01), Cook et al.
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patent: 2004/0150118 (2004-08-01), Honda
patent: 2008/0057625 (2008-03-01), Chan et al.

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