Semiconductor chip package structure

Details Semiconductor chip package structure Semiconductor chip package structure

2008-11-05

2010-06-15

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257SE23020

Reexamination Certificate

active

07737541

ABSTRACT:
A semiconductor chip package structure is described. The semiconductor chip package structure comprises a first chip, which is operated through a first power connection, having a central region and a marginal region. The first chip comprises a plurality of first and second power bonding pads disposed in a marginal region on the top of the first chip. A first power ring and a second power ring are disposed on the first chip, wherein the first and second power rings are respectively electrically connected to the first and second power bonding pads. A second chip, which is operated through a second power connection, is mounted on the central region of the first chip, wherein the second chip comprises a plurality of power bonding pads thereon. A plurality of second bonding wires are electrically connected to the power bonding pads and the second power bonding pads, respectively.

REFERENCES:
patent: 2008/0237645 (2008-10-01), Uchino

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