Semiconductor chip package configuration and method for facilita

Details Semiconductor chip package configuration and method for facilita Semiconductor chip package configuration and method for facilita

1987-11-03

1989-01-03

Sikes, William L.

Electricity: conductors and insulators

Feedthrough or bushing

Compression

357 74, 357 69, 357 80, 174 52FP, 174 52R, 361421, 324158F, 339 17C, 339 17CF, 339 17LC, H01L 2348, H02G 1308

Patent

active

047960809

ABSTRACT:
A semiconductor chip package configuration and a method are disclosed for facilitating testing of the chip package and mounting of the chip package on a substrate by forming one or more lead alignment bars in interconnecting relation with adjacent leads on the chip package, the lead alignment bars being formed from a material providing electrical isolation between leads during testing of the chip package and for providing physical spacing between the leads both during testing and later mounting of the chip package on the substrate so as to prevent adjacent leads from inadvertent contact. Preferably, the lead alignment bars are formed from a high resistivity material selected to provide sufficient conductivity between the interconnected leads for minimizing electrostatic discharge conditions therebetween, the material being sufficiently non-conductive to permit functional and dynamic testing of the leads. After testing of the chip package, it is mounted on the substrate with the interconnecting lead alignment bars then being removed to facilitate subsequent operation of the chip package.

REFERENCES:
patent: 3444440 (1969-05-01), Bell et al.
patent: 3444441 (1969-05-01), Helda et al.
patent: 3611061 (1971-10-01), Segerson
patent: 4204317 (1980-05-01), Winn
patent: 4463217 (1984-07-01), Orcutt
patent: 4466183 (1984-08-01), Burns
Jerry Lyman, "Surface Mounting Alters the PC-Board Scene", Electronics, Feb. 9, 1984, pp. 113-116.

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