Semiconductor chip package assembly method and apparatus for...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Metallic housing or support

Reexamination Certificate

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C438S121000, C438S123000, C257S670000, C257S675000, C257S707000, C257SE23104

Reexamination Certificate

active

08008131

ABSTRACT:
The invention provides semiconductor chip packages, tools, and methods for preventing and for correcting leadfinger deformation caused during wirebonding in semiconductor chip package manufacturing. Disclosed are improved heat blocks and methods for their use in ensuring adequate clearance between leadfingers and adjacent heat spreaders, as well as semiconductor chip package assemblies wherein a selected clearance between leadfingers and parallel surfaces may be assured. Methods of the invention include steps for supporting the proximal ends of the leadfingers using the wirebonding cavity of a heat block. Thus supported, a plurality of bondwires are attached to couple bond pads of the semiconductor chip to the proximal ends of leadfingers. Thereafter, the clearance between the wirebonded proximal ends of the leadfingers and the adjacent parallel surface of the heat spreader is adjusted using a spacing cavity of the heat block. In preferred embodiments of the invention, a plurality of bondwires couple a plurality of bond pads of the semiconductor chip to the proximal end of a single leadfinger, with assured clearance between the proximal end of the leadfinger and an underlying surface.

REFERENCES:
patent: 5666003 (1997-09-01), Shibata et al.
patent: 6404048 (2002-06-01), Akram
patent: 6924549 (2005-08-01), Nose et al.
patent: 2003/0183907 (2003-10-01), Hayashi et al.
patent: 2005/0218194 (2005-10-01), Suzuki
patent: 2000150582 (2000-05-01), None
patent: 20000014537 (2000-07-01), None

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