Semiconductor chip package and multichip package

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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Details

C257S686000, C257S723000, C257S784000, C257SE23141

Reexamination Certificate

active

07576431

ABSTRACT:
The present invention provides a multichip package wherein a plurality of semiconductor chip packages (100) in each of which first electrode pads (16a) provided in a main surface of a semiconductor chip, and first bonding pads (20a) and first central bonding pads (18a) formed in an upper area of the main surface are respectively electrically connected by first redistribution wiring layers (24) in a one-to-one correspondence relationship, and second electrode pads (17b), and second bonding pads (22b) and second central bonding pads (18b) formed in an upper area of the main surface are respectively electrically connected by second redistribution wiring layers (26) in a one-to-one correspondence relationship, are stacked on one another.

REFERENCES:
patent: 6376904 (2002-04-01), Haba et al.
patent: 6414381 (2002-07-01), Takeda
patent: 6569709 (2003-05-01), Derderian
patent: 6885093 (2005-04-01), Lo et al.
patent: 6965160 (2005-11-01), Cobbley et al.
patent: 2001/0031513 (2001-10-01), Masuda et al.
patent: 2002/0096755 (2002-07-01), Fukui et al.
patent: 2002/0195697 (2002-12-01), Mess et al.
patent: 2001-007278 (2001-01-01), None
patent: 2001-196529 (2001-07-01), None
patent: 2001-298150 (2001-10-01), None
patent: 2002-110898 (2002-04-01), None

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