Semiconductor chip package and method of fabricating same

Details Semiconductor chip package and method of fabricating same Semiconductor chip package and method of fabricating same

2005-02-15

2005-02-15

Zarabian, Amir (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Housing or package filled with solid or liquid electrically...

C257S690000, C257S706000, C257S762000

Reexamination Certificate

active

06856011

ABSTRACT:
A semiconductor chip package and a method of fabricating a semiconductor chip package provide a reduced chip size package. The semiconductor chip package includes a semiconductor chip; a plurality of pads disposed on an upper surface of the semiconductor chip; a thermosetting resin formed on the upper surface of the semiconductor chip such that through-holes in the thermosetting resin expose the pads; a multi-layer wiring pattern formed on the thermosetting resin; a connecting unit electrically connecting the multi-layer wiring pattern with the pads; a solder resist on the thermosetting resin, the multi-layer wiring pattern and the connecting unit, such that at least one through-hole in the solder resist exposes a portion of the multi-layer wiring pattern; and a solder ball mounted on the through-hole of the solder resist in contact with the exposed portion of the metal pattern.

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patent: WO 9840915 (1998-09-01), None

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