Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Making plural separate devices
Reexamination Certificate
1999-05-24
2002-12-10
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Making plural separate devices
C438S118000, C438S612000, C438S613000, C257S690000, C257S700000, C257S773000
Reexamination Certificate
active
06492200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip package, and in particular to a semiconductor chip package and a fabrication method thereof which can consecutively fabricate a semiconductor chip to the package.
2. Description of the Background Art
Many companies have made every effort to fabricate a highly-integrated pin package. There is exemplified a BGA-type semiconductor package using a plurality of solder balls bonded to a substrate as outer terminals. Here, the BGA-type semiconductor chip package is fabricated by positioning the plurality of solder balls at an upper or lower surface of the substrate, and by bonding the solder balls at a time with a heat from a furnace, and thus productivity is improved. In addition, the outer terminals are ball-shaped, and thus are not easily deformed due to an external shock.
The constitution of the conventional BGA-type semiconductor chip package will now be explained with reference to the accompanying drawings.
Referring to
FIG. 1
, an elastomer
2
is bonded to an upper center portion of a semiconductor chip
1
. An adhesive resin
3
is formed on the elastomer
2
. A plurality of conductive metal traces
4
a
transmitting an electric signal between our terminals and semiconductor chip pads are bonded to the adhesive resin
3
. Each one end portion of the conductive metal traces
4
a
is connected to a metal lead
4
b
. The metal lead
4
b
is connected to a pad
6
formed at an upper edge portion of the semiconductor chip
1
. A solder resist
5
is spread at the portion of the conductive metal trace
4
a
where a conductive ball is not bonded, and an upper portion of the adhesive resin
3
. An encapsulant
7
covers the metal leads
4
b
and the upper portion of the semiconductor chip
1
which the solder resist
5
is not spread. The conductive ball
8
is formed on the conductive metal trace
4
a
, and serves as an outer terminal.
A method of fabricating the conventional BGA-type semiconductor package as depicted in
FIG. 1
will now be described.
Firstly, a plurality of semiconductor chips are formed on a wafer in accordance with a general method of fabricating a semiconductor device. Polyimide or benzocyclo butene (BCB) is spread at the upper portions of the semiconductor chips as a passivation film. Thereafter, pads of the semiconductor chips are exposed. A dicing process for respectively cutting the plurality of semiconductor chips on a wafer is carried out. An elastomer is bonded to an upper portion of a polyimide tape. An adhesive is formed at the upper and lower surfaces of the elastomer, and a plurality of metal patterns are formed at the lower surface of the polyimide tape. A die attach process is performed for bonding the elastomer to the upper surface of the semiconductor chips. The upper surface where the pads are formed. A metal lead is connected at the end portion of the metal pattern. In addition, the plurality of metal patterns are mostly covered with a solder resist, and partially exposed. A solder ball is mounted at the exposed portion of the metal pattern.
Thereafter, a resultant structure of the die attach process is turned over.
Then, a lead bonding process is performed thereon for bonding one end portion of the metal lead to the pad of the semiconductor chip. An encapsulation process is carried out in order to cover the metal lead and the upper portion of the pad of the semiconductor chip.
Then, a solder ball mounting process is performed for mounting the solder ball at the upper portion of the metal patterns (exposed portions which are not spread with the solder resist) formed at the polyimide tape. A reflow process of the solder ball is carried out for bonding the solder balls to the metal patterns. Thus, the fabrication of the conventional BGA-type semiconductor chip package is completed.
However, the BGA-type semiconductor package as shown in
FIG. 1
has many disadvantages in that the fabrication method is complicated and includes many process steps, the fabrication time of the package is long, and the fabrication cost is high. That is, after the process of forming the semiconductor device is carried out, the process of respectively separating the chips by cutting the wafer, the die attach process, the bonding process of the metal lead and the solder ball mounting process are performed.
In addition, each process requires different package fabrication equipment, which results in increased cost.
In accordance with the conventional semiconductor chip package process, after the semiconductor chips are each respectively cut, and thus the chips are assembled to package one by one. As a result, a process time becomes longer, and productivity is decreased.
Also, it is necessary to prepare for the film-type elastomer and the polyimide tape having its one side provided with the metal patterns, thereby increasing the raw material cost. Therefore, the package cost is also increased.
In general, an FR-4 is used for a material of a printed circuit board where the semiconductor chip and a silicon substrate is used for the semiconductor chip material. The FR-4 and the silicon has a high elastic modulus and there is big difference in thermal expansion coefficient between the FR-4 and the silicon substrate. In addition, a polyimide layer having a high elastic modulus is employed as the passivation film to be formed at the upper surface of the conventional semiconductor chip. Accordingly, when the semiconductor chip is mounted on the printed circuit board, the polyimide layer cannot absorb a stress generated due to the big difference in the thermal expansion coefficient between the printed circuit board and the semiconductor chip. As a result, the stress is applied to a solder between the outer lead and the printed circuit board, thus decreasing a life span of the semiconductor package.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a semiconductor chip package and a fabrication method thereof which can reduce a package fabrication time by consecutively fabricating a semiconductor chip to the semiconductor package at a wafer level.
It is another object of the present invention to provide a semiconductor chip package and a fabrication method thereof which can reduce a fabrication cost because the package is fabricated by equipment used for fabricating a semiconductor chip and an additional cost of equipment for the package is not incurred.
It is still another object of the present invention to provide a semiconductor chip package and a fabrication method thereof which can improve reliability by employing a silicone having a relatively lower elastic modulus than a polyimide layer as a passivation film for a semiconductor chip, in order to absorb a stress generated due to a big difference in thermal expansion coefficient between the semiconductor chip and a printed circuit board.
It is still another object of the present invention to provide a semiconductor chip package and a fabrication method thereof which can improve reliability by spreading a material having a relatively high elastic modulus on a silicone which is a low elastic modulus material, and on the metal patterns formed on the silicone, in order to absorb a stress applied to the metal patterns.
In order to achieve the above-described objects of the present invention, there is provided a semiconductor chip package including: a semiconductor chip, a plurality of pads being formed at its upper portion; a low elastic modulus material layer covering the semiconductor chip except the pads, and having a relatively low elastic modulus; a plurality of metal patterns connected with at least one pad, and formed on the low elastic modulus material layer; a high elastic modulus material layer covering the metal patterns and the low elastic modulus material layer, having an opening portion for at least partially exposing the metal patterns, and having a relatively higher elastic modulus than the low elastic modulus material layer; and electric media bonded to the upper
Kang In Soo
Park Ik Seong
Fleshner & Kim LLP
Hyundai Electronics Industries Co., Inc.
Picardat Kevin M.
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