Semiconductor chip package and fabrication method thereof

Details Semiconductor chip package and fabrication method thereof Semiconductor chip package and fabrication method thereof

1999-10-12

2001-08-21

Picardat, Kevin M. (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S455000, C438S613000

Reexamination Certificate

active

06277670

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a package and a fabrication method thereof, and in particular, to an improved integrated chip package and the fabrication method thereof.
2. Background of the Related Art
FIG. 1
is a perspective view showing a partly cut away PMEB (Plastic Molded Extended Bump) type chip-size semiconductor package. As shown in this drawing, a metal wiring pattern
13
is formed to connect a plurality of chip pads
12
formed on the semiconductor chip
11
with internal bump bonding pads
17
. Conductive internal bumps
16
are attached on the internal bump bonding pad
17
and tapes (not shown) are attached to the top surfaces of the conductive internal bumps
16
. Then the semiconductor chip
11
is surrounded and molded with a molding resin
14
. When the tapes are removed, the top surfaces of the internal bumps
16
are exposed. A solder paste is applied on the internal bumps
16
, external electrode bumps
15
are placed thereon and the external bumps
15
and the internal bumps
16
are attached through an infrared reflow process, resulting in a completed PMEB-type chip-size semiconductor package, a description of which was published at the “SEMICON JAPAN '94 SYMPOSIUM” held by the MITSUBISHI corporation in Japan.
FIG. 2
is a cross-sectional view of a bump electrode in FIG.
1
. The chip pads
12
are formed on the top surface of the semiconductor chip
11
, and a passivation film
18
is formed on the semiconductor chip
11
, except on the top surface of the chip pads
12
. The metal wiring pattern
13
is formed on the chip passivation film
18
, wherein one end of the metal wiring pattern
13
is connected to the chip pad
12
and the other end thereof
13
is connected to the internal bump bonding pad
17
. A polyimide film
10
is formed on the above construction, except at the internal bump connecting pads
17
, and the internal bumps
16
are attached to the exposed internal bump connecting pads
17
by means of a solder adhesive
20
composed of Pb or Sn. A molding resin
14
encapsulates the semiconductor chip
11
by surrounding the same on the entire surface of the above construction except for the top surface of the internal bumps
16
, and the external bumps
15
are attached to the internal bumps
16
.
As described above, a bump bonding pattern for transmitting an electrical signal of the chip pads
12
to the external bumps
15
is formed through a separate formation process of a metal wiring pattern (a pre-assembly process). The metal wiring pattern
13
is formed from the chip pads
12
of the semiconductor chip
11
to the internal bump connecting pads
17
to be electrically connected, respectively, and the conductive internal bumps
16
are attached to the internal bump connecting pads
17
. The molding resin
14
surrounds and seals the above entire construction, and the external bumps
15
, serving as external leads, are attached to the internal bumps
16
to form a completed chip-size semiconductor package. Although the PMEB-type chip-size semiconductor package allows the overall size of the entire semiconductor package to be smaller, a separate formation process for the metal wiring pattern (pre-assembly process in the published data) and an bonding process for internal and external bumps are necessary. Further, the fabrication process is complicated and the fabrication cost is increased.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to solve the problems of the related art.
An object of the present invention is to minimize the size of a semiconductor package.
Another object of the present invention is to facilitate the provision of numerous pins of a package.
Another object of the present invention is to simplify the fabrication process.
A further object of the present invention is to enhance the electrical characteristics of the chip package.
Still another object of the present invention is to form the shortest conductive or electrical path for transmitting signals sent from the chip pads of the integrated circuit.
To achieve the above object, there is provided a semiconductor chip package, comprising a semiconductor chip having a plurality of chip pads formed thereon; a passivation film formed on the semiconductor chip with the chip pads exposed; a plurality of metal wirings coupled to the chip pads on the passivation film; external balls electrically connected to the metal wirings; and a molding resin layer formed on a first surface of the semiconductor chip such that upper portions of the external balls protrude from the molding resin layer.
To achieve the above object, there is provided an improved fabrication method for making a semiconductor package, comprising the steps of forming a passivation film on a first surface of a wafer such that a plurality of chip pads of the wafer are exposed; forming a metal layer on the passivation film; forming a patterned photoresist layer on the metal layer, etching the metal layer by using the photoresist layer as a mask, stripping the photoresist layer and forming a patterned metal wiring conductively coupled to the plurality of chip pads; printing a solder paste on each metal wiring, mounting a solder ball, performing an infrared reflow process, removing a remaining solder paste, and attaching the solder ball serving as an external ball to each metal wiring; forming a molding resin layer on the wafer and metal wiring by performing a first molding process with a resin such that an upper portion of the solder ball is exposed; carrying out a foil mounting on a second surface of the wafer; and cutting the wafer into a semiconductor chip package.
To achieve such objects, advantages and features in part or in whole, the present invention includes a chip package, comprising an integrated chip having a plurality of chip pads on a first surface; a passivation film formed on the first surface of the integrated chip with the plurality of chip pads exposed; a plurality of conductive wires formed on the passivation film such that a corresponding conductive wire is conductively coupled to a corresponding chip pad; a plurality of conductive media, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wire; and a molding layer formed on the plurality of conductive wires, the molding layer having a prescribed thickness which is less than the prescribed height such that portions of the plurality of conductive media protrude from the molding layer.
The present invention may be achieved in whole or in part by a method for fabricating a chip package comprising the steps of: a) forming a passivation film on a wafer having a plurality of individual integrated chips with a plurality of chip pads exposed on a first surface of the plurality of individual integrated chips; b) forming a plurality of conductive wires on the first surface of each individual integrated chip to couple corresponding chip pads to corresponding conductive wires; c) forming a plurality of conductive media, each having a first prescribed height and a corresponding conductive media being formed on a corresponding conductive wires of each individual integrated chip; and d) forming a molding layer on the plurality of conductive wires, the molding layer having a prescribed thickness which is less than the prescribed height such that portions of the plurality of conductive media protrude from the molding layer of each individual integrated chip.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appe

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