Semiconductor chip module interconnection system

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357 82, 357 80, 357 74, H01L 2348, H01L 2352, H01L 2340, H01L 2312

Patent

active

046672206

ABSTRACT:
A module for a semiconductor chip having a front face with a two dimensional array of power, ground and signal contacts is disclosed. Power, ground and signal conductors extend from the respective contacts on the front face of the chip. A pair of electrically conductive plates are parallel to the front face of the chip and located at the termination of the conductors. The plate nearer the conductors is electrically coupled to either the power or ground conductors, and contains apertures corresponding to the remaining ground or power conductors and to the signal conductors. A plurality of discrete signal transmission members are located at a surface of the plate farther from the conductors. The ground or power conductors not connected to the near plate are electrically coupled to the far plate through certain of the apertures, and the signal conductors are coupled to the respective signal transmission members through the remaining apertures.

REFERENCES:
patent: 4407007 (1983-09-01), Desai et al.
patent: 4551747 (1985-11-01), Gilbert et al.
"Microelectronic Packaging"--Blodgett, Jr.--Scientific American Magazine, Jul. 1983, vol. 249, No. 1, pp. 88-96.
"Integrated Circuit Package and Heat Sink--Tiffany--IBM Technical Disclosure Bulletin--Tiffany--vol. 13, No. 1, Jun. 1970, p. 58.
"Electrically Conductive Array in an Elastomeric Material"--Newmann et al.--IBM Technical Disclosure Bulletin, vol. 25, No. 4, Sep. 1982, p. 1801-1802.
"Distribution System for Multilayer Ceramic Modules"--Markewycz--IBM Technical Disclosure Bulletin-vol. 19, No. 4, Sep. 1976, pp. 1270-1271.

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