Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2003-09-11
2004-07-06
Flynn, Nathan J. (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S125000, C438S126000, C438S127000
Reexamination Certificate
active
06759270
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to a structure and method of making the same for a semiconductor chip module; and, more particularly, to a structure and method for forming a semiconductor chip module which eliminates the need for C4 connections of an I/C chip to a carrier by allowing circuitry to be formed directly on a sheet laminated to the I/C chip without the necessity of having C4 connections of a chip to a carrier.
BACKGROUND OF THE INVENTION
Background Information
One conventional prior art technique of mounting integrated circuit chips to printed circuit boards involves the use of a chip carrier. In this technique, the integrated circuit chip is provided with electrical contact pads and the chip is mounted to a chip carrier by means of solder connection to the carrier directly to the chip pads known as C4 technology (control collapse chip connection). The chip carrier includes fan-out circuitry, conventionally multilayer circuitry, formed on dielectric materials and on which the chip is mounted and has ball grid array pads which are suitable for connecting a chip carrier by solderball connections to a printed circuit board. Thus, the connection of the chip to the circuit board is first through C4 connections to the chip carrier, and the chip carrier then includes a multilayer structure having output circuitry terminating in ball grid array pads which are connected by solderball connections to pads on the printed circuit board. In some cases, the chip carrier may mount more than one chip, in which case the connection of one chip to another on the same carrier, if required, can be done through the chip carrier. However, in many instances, but a single chip is mounted on a chip carrier and, in order for the chips to communicate with each other, the communication must be through the C4 joints to the fan-out circuitry on the chip carrier on which the first chip is mounted, through the ball grid array to the printed circuit board, then back to the ball grid array connected to the chip carrier to which the second chip is attached, and, thence, through the C4 joints of the second chip carrier to the second chip. Such a long path utilizing a significant amount of wiring area is one drawback to the prior art invention where multiple chips are mounted each on an individual chip carrier and must be connected to each other. Furthermore, a longer wiring path diminishes communication speed.
Another drawback to the conventional prior art C4 technology is the propensity of failure to occur at the C4 joints due to thermal mismatch and other factors. This is especially true as the technology produces finer line circuitry and more pads in a particular footprint, thus reducing the size of the C4 connections and, hence, contributing to such failure.
There have been several prior art proposals to eliminate the C4 technology type of connection, but these have suffered drawbacks in that they are relatively non-cost effective except for high end modules and/or induced stresses at certain locations, so these solutions are not viable. Thus, there is a need for a cost effective integrated circuit chip module which eliminates the necessity of C4 connections.
SUMMARY OF THE INVENTION
According to the present invention, a semiconductor chip module and method of forming the module is provided. The module includes a support member having at least one well formed therein and being open to receive a semiconductor chip. Each of the wells is of a depth substantially equal to the thickness of a semiconductor chip. The support member has a planar region surrounding each of said wells. A semiconductor chip is disposed in each well with each semiconductor chip having electrical contact pads on one side thereof oriented toward the opening of the well in which it is disposed. A dielectric sheet of material is laminated over each of the semiconductor chips extending at least partially onto the planar area surrounding the wells and having a first face oriented away from the semiconductor chip. Electrical circuitry is formed on the first face of the dielectric sheet and extends onto the sheet that overlies the planar region. The electrical circuitry has electrical capture pads thereon. Conducting vias are formed in the dielectric sheet of material connecting the electrical circuitry on the dielectric sheet of material with the contact pads on the chip. A multilayer, circuitized laminate structure is provided having contact pads on one face thereof aligned with the capture pads on the dielectric sheet, and the second circuitry on the opposite face of the circuitized laminate structure connected to a ball grid array structure. Thus, a chip mounted in a support structure is provided having fan-out circuitry from the electric contact pads on the chip to the ball grid array structure without the necessity of having C4 connections to a chip carrier.
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IBM Technical Disclosure Bulletin entitled “Flatpack Package Using Core Metal Layer of Composite Substrate as Ground Plane”, Mar., 1991.
Infantolino William
Markovich Voya R.
Sathe Sanjeev B.
Thiel George H.
Flynn Nathan J.
Hogg William N.
International Buisness Machines Corporation
Roman Angel
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