Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2000-02-07
2003-09-23
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S126000, C257S668000
Reexamination Certificate
active
06624008
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor chip package such as a ball (or bump) grid array (BGA) package, particularly a semiconductor chip mounting tape, and also to a semiconductor device, and fabricating methods.
2. Description of Related Art
In BGA packages, circuit patterns are formed on both sides of a substrate (or a tape) and a semiconductor chip is mounted on the surface of the substrate.
For the electrical connection of the semiconductor chip mounted on the substrate, pads formed on the semiconductor chip and leads formed on the surface of the substrate are electrically connected by wire bonds (or bumps in the case of a flip chip system) and a connecting portion is protected by a resin seal formed by a method such as molding, potting, or the like.
Solder balls serving as external connecting terminals are formed on the circuit pattern on the back side of the substrate in accordance with a predetermined layout pattern.
The solder ball is temporarily fixed to a predetermined position by a ball mounter by using a flux, thereafter, reflowed through a furnace, and fixedly bonded onto the substrate, thereby forming the external connecting terminal.
With regard to the external connecting terminals, the diameter of the ball is reduced due to demands for miniaturization of the package and use of multi-pins, and the adoption of a narrower pitch of terminals is also occurring.
FIG. 1
is a cross sectional view showing a state where a solder balls are held by vacuum at a vacuum plate of the conventional ball mounter. The mounting of solder balls
1
by the ball mounter is performed by using the vacuum plate
2
.
Vacuum holes
4
having tapered portions
3
are formed in the vacuum plate
2
in accordance with the layout pattern of the pads on the back side of the substrate, thereby holding the solder balls
1
by vacuum evacuating by an apparatus (not shown).
The solder balls
1
are subsequently deposited on the substrate by a method whereby a flux
5
is transferred to the solder balls
1
and the solder balls
1
are temporarily fixed onto the pads of the substrate by an adhering force of the flux
5
.
However, a problem occurs in that the diameter of the solder ball
1
decreases and the flux
5
transferred to the solder ball
1
is deposited to the tapered portion
3
of the vacuum plate
2
. As a result, separation of the solder balls
1
from the vacuum plate
2
is disturbed or hindered by the flux, and the solder ball
1
cannot be deposited surely onto the pad of the substrate.
When, on the other hand, the solder balls
1
have a reduced diameter, the transfer amount of the flux to the solder ball
1
decreases, so that fouling such as an oxide film on the pad of the substrate cannot be sufficiently removed by the flux. This will result in degrading of the fusing state of the solder at the time of the reflow process. Thus, there also is a problem that the solder ball
1
drops because the solder is insufficiently fused.
OBJECTS AND SUMMARY OF THE INVENTION
To solve the above problems, according to the invention, post portions to be connected to semiconductor chips are formed on a first surface of a tape having an insulation characteristic, which will be referred to as insulation tape, external connecting terminals are formed on a second surface of the insulation tape, and the post portions and the external connecting terminals are integrally formed by solder balls piercing through holes formed in the insulation tape.
REFERENCES:
patent: 4530896 (1985-07-01), Christensen et al.
patent: 4945634 (1990-08-01), Kumada
patent: 4977441 (1990-12-01), Ohtani et al.
patent: 5684328 (1997-11-01), Jin et al.
patent: 5696032 (1997-12-01), Phelps et al.
patent: 5990545 (1999-11-01), Schueller et al.
patent: 6199273 (2001-03-01), Kubo et al.
patent: 6258632 (2001-07-01), Takebe
patent: 64-72537 (1989-03-01), None
patent: 5-315405 (1993-11-01), None
Geyer Scott B
Kunitz Norman N.
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