Semiconductor chip high density packaging

Details Semiconductor chip high density packaging Semiconductor chip high density packaging

1995-10-10

1997-02-18

Mintel, William

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

257686, 257723, H01L 2302

Patent

active

056043775

ABSTRACT:
A packaging scheme for a stack of semiconductor chips that is light weight and has better cooling and mechanical and electrical protection than that hitherto provided for. The stack of semiconductor chips are connected to a wiring interface. Separating each of the chips from any adjacent chip is a supporting, insulating interposer. Each interposer electrically insulates each chip from any adjacent chip while mechanically protecting the chip supported thereby. The interposers are the cantilevered shelves of a rack and they prevent undue mechanical movement of the chips while still permitting for convection cooling of the chips. An hermetically sealed enclosure around the stack of chips, can be provided with a cooling fluid therein and completes the package. In another arrangement, the rack is itself is provided with circuitry which may be coupled to the chips positioned and supported therein.

REFERENCES:
patent: 4996587 (1991-02-01), Hinrichsmeyer et al.
patent: 5030110 (1991-07-01), Groves et al.
patent: 5128831 (1992-07-01), Fox, III et al.
patent: 5172303 (1992-12-01), Bernardoni et al.
patent: 5239199 (1993-08-01), Chiu
patent: 5327327 (1994-07-01), Frew et al.
patent: 5909305 (1992-05-01), Dunaway et al.

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