Active solid-state devices (e.g. – transistors – solid-state diode – Alignment marks
Reexamination Certificate
2008-09-18
2010-10-12
Potter, Roy K (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Alignment marks
C257S737000, C257SE23179
Reexamination Certificate
active
07812465
ABSTRACT:
Disclosed is a semiconductor chip having an alignment mark which is formed on the surface of the semiconductor chip where no external connection bump is formed, and which has the position information of the external connection bump. A method of manufacturing the semiconductor chip having an alignment mark is also provided. Because the semiconductor chip includes the alignment mark having the position information of the external connection bump, the external connection bump is matched with a via which is formed in the external circuit layer of a printed circuit board including the semiconductor chip, thus improving electrical connection with the printed circuit board, and increasing the reliability of the printed circuit board including the semiconductor chip.
REFERENCES:
patent: 6278193 (2001-08-01), Coico et al.
patent: 6476499 (2002-11-01), Hikita et al.
patent: 6617702 (2003-09-01), Hsu et al.
patent: 6938335 (2005-09-01), Kuribayashi et al.
Chung Yul Kyo
Lee Jae Kul
Potter Roy K
Samsung Electro-Machanics Co., Ltd.
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