Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – With particular signal path connections
Reexamination Certificate
2005-03-22
2005-03-22
Wille, Douglas (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Gate arrays
With particular signal path connections
C257S210000
Reexamination Certificate
active
06870206
ABSTRACT:
A semiconductor chip has standard cells arranged in a plurality of mutually adjacent rows. Each standard cell is connected by a plurality of tracks for connection to other elements of the semiconductor chip and/or terminals of the semiconductor chip. The power supply tracks of the standard cells of at least one row of standard cells are shortened in such a way that the tracks terminate in the region of a standard cell at the edge of the row.
REFERENCES:
patent: 4870300 (1989-09-01), Nakaya et al.
patent: 5468977 (1995-11-01), Machida
patent: 5635737 (1997-06-01), Yin
patent: 42 39 463 (1993-05-01), None
patent: 60 123 144 (1985-08-01), None
patent: 60 153 144 (1985-08-01), None
patent: 62 152 141 (1987-07-01), None
patent: 02 201 958 (1990-08-01), None
patent: 02 224 370 (1990-09-01), None
patent: 04 075 370 (1992-03-01), None
patent: 05 055 379 (1993-03-01), None
patent: 05 343 653 (1993-12-01), None
patent: 07 321 295 (1995-12-01), None
patent: 410261780 (1998-09-01), None
Selz Manfred
Wagner Michael
LandOfFree
Semiconductor chip, fabrication method, and device for... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor chip, fabrication method, and device for..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor chip, fabrication method, and device for... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3422193