Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2002-07-02
2003-11-18
Tran, Thien (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S533000, C257S534000, C257S535000, C257S690000
Reexamination Certificate
active
06649999
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor chip configuration with a substrate on which a layer sequence is constructed with functional elements that can be contacted by way of contact pads, whereby conductive tracks run in a rewiring layer from the pads to contact elevations.
The invention further relates to a method for constructing contacts on a semiconductor chip configuration.
Owing to the contact elevations, such semiconductor chips can be mounted directly on PCBs. The contact elevations contact the contacts on the PCB. Accordingly, the spacings between the contact elevations are selected so that they correspond to the spacings between the contacts on the PCB. On the semiconductor chip side, the contact elevations are connected in a rewiring layer to contact points (pads), which are connected to the functional elements in the layer sequence. Each conductive track leads from a respective contact elevation to a respective pad.
The pads are usually designed such that they are suitable for bonding and contacting with test cards which are equipped with pins. The contact pads consequently occupy a relatively large area of some 90 &mgr;m×90 &mgr;m.
In addition, trimming capacitors are arranged under the pads in the semiconductor chip, which serve to adapt the capacity of the pads to the prescribed specifications. A plurality of trimming capacitors are usually provided. The values for the capacity are adjusted by replacing the mask for a metal layer in a specified lithography step.
Conventional pads require an appreciable proportion of chip space. In addition, the trimming of the capacitors is difficult and is no longer possible after fabrication.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor chip configuration and a corresponding fabrication method, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which provides for an improved semiconductor chip configuration and an improved method for constructing contacts on it.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor chip configuration, comprising:
a substrate carrying a layer sequence with electronic functional elements and including a rewiring layer on the substrate;
contact pads formed as vias connected to the functional elements;
contact elevations;
conductive tracks extending in the rewiring layer from the contact pads to the contact elevations;
each of the conductive tracks widening in a portion remote from the respective the via to form a bottom electrode of a respective capacitor to which the via is connected; and
the capacitor further including an insulation layer arranged over the bottom electrode, and a top electrode above the insulation layer.
In accordance with an added feature of the invention, the insulation layer and the bottom electrode are disposed between the substrate and the top electrode.
In accordance with an additional feature of the invention, the top electrodes of the capacitors form a contiguous metal layer.
In accordance with another feature of the invention, the top electrodes of the capacitors of the semiconductor chip configuration are connected to a common contact elevation.
With the above and other objects in view there is also provided, in accordance with the invention, a method of producing contacts in a semiconductor chip configuration, which comprises:
constructing electronic functional elements on a substrate; forming vias for contacting the electronic functional elements;
constructing conductive tracks in a rewiring layer connected to the vias, and connecting the conductive tracks to capacitors remote from the vias; and
wherein the conductive tracks are widened into a widened portion to form a respective bottom electrode of the capacitors, and an insulation layer is formed over the respective widened portions of the conductive tracks, and a top electrode is formed thereabove.
Because the pads are constructed as vias, they occupy a negligible proportion of chip space, namely 0.005%, as opposed to 0.6% in the prior art. Furthermore, the trimming capacitors are no longer located in the functional layers or in the wiring layers within the chip which adjoin the functional layers; rather, they are located in the rewiring planes over the functional layers, and consequently additional space is opened up in the underlying wiring planes and functional planes.
In a preferred embodiment of the invention, the capacitors that are allocated to the conductive tracks are constructed such that an electrode of the capacitors is positioned on the surface of the semiconductor chip.
The advantage of this configuration is that the electrode on the surface of the semiconductor chip can be post-trimmed. In other words, the top electrodes can configured to respectively adapt the capacitor to a predetermined capacitance value. Specifically, the capacitors can be trimmed subsequent to a function test of the functional elements.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a semiconductor chip configuration and a fabrication method, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.
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patent: 5789303 (1998-08-01), Leung et al.
patent: 5994169 (1999-11-01), Lamson et al.
patent: 03 138 962 (1991-06-01), None
patent: 11 145 394 (1999-05-01), None
patent: 2000 323 664 (2000-11-01), None
Yasunaga, M. et al.: Chip Scale Package: “A Lightly Dressed LSI Chip”, IEEE, vol. 18, No. 3, Sep. 1995, pp. 451-457.
Mayback Gregory L.
Tran Thien
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