Semiconductor chip, chip stack package and manufacturing method

Details Semiconductor chip, chip stack package and manufacturing method Semiconductor chip, chip stack package and manufacturing method

2005-02-01

2005-02-01

Ngo, Hung V. (Department: 2831)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C257S777000

Reexamination Certificate

active

06849802

ABSTRACT:
A semiconductor chip has connection lines that are routed to the side surface from bump pads on the back surface of the chip. Such semiconductor chips are stacked on a circuit board to form a chip stack package while bumps are interposed between the bump pads of the lower chip and bonding pads of the upper chip. Further, an interconnecting member such as a conductive adhesive or a wiring board is applied to the side surfaces of the stacked chips such that the connection lines are connected to the interconnecting member. Therefore, the centrally disposed bonding pads of the chips are electrically connected to the circuit board through the bumps, the bump pad, the connection lines and the interconnecting member. The semiconductor chip may have heat dissipation part formed on the back surface. Methods of manufacturing the semiconductor chip and the chip stack package are also provided.

REFERENCES:
patent: 5394303 (1995-02-01), Yamaji

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