Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-02-07
2002-11-05
Weiss, Howard (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S797000
Reexamination Certificate
active
06476499
ABSTRACT:
This application is based on application Nos. 11-30478, 11-30479, 11-30480, 11-38794 and 11-47078 filed in Japan, the contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor chips for a so-called chip-on-chip structure which includes a plurality of semiconductor chips bonded in a double-stacked relation, chip-on-chip semiconductor devices, and chip-on-chip mounting methods.
2. Description of Related Art
For size reduction and higher integration of semiconductor devices, a proposal has been made to shift the design concept from a conventional two-dimensional structure to a three-dimensional structure.
However, production of semiconductor devices of three-dimensional structure through a continuous process often encounters difficulties such as a lower yield.
The inventors of the present invention have been conducting studies on practical applications of a semiconductor device of a so-called chip-on-chip structure which includes a plurality of semiconductor chips bonded to one another in a face-to-face double-stacked relation.
Where semiconductor chips are bonded to each other in a stacked relation, for example, where a relatively small secondary chip is laid on the front face of a relatively large primary chip, the secondary chip can easily be positioned in alignment with the primary chip with the front face thereof upward and with the back face thereof opposed to the front face of the primary chip.
However, if an attempt is made to stack the primary chip and the secondary chip in a face-to-face relation, there is a difficulty in aligning these semiconductor chips with each other. This is because the orientation of a semiconductor chip, the arrangement of electrodes on the front face of the semiconductor chip and the like cannot be checked from the back side thereof.
Particularly, the electrodes are not always arranged in a predetermined positional relationship with the profile of the semiconductor chip, but the positional relationship between the electrode arrangement and the profile varies depending on dicing conditions under which a semiconductor wafer is diced into semiconductor chips. Therefore, it is difficult to align or position the semiconductor chips with respect to each other by viewing either of the semiconductor chips from the back side thereof.
Even if the primary and secondary chips have substantially the same size, the alignment of the semiconductor chips for bonding thereof is difficult.
SUMMARY OF THE INVENTION
In view of the foregoing, it is a principal object of the present invention to provide a chip-on-chip structure which includes a plurality of semiconductor chips bonded to one another in a face-to-face stacked relation for practical applications.
It is another object of the invention to provide a semiconductor chip for chip-on-chip mounting to provide the chip-on-chip structure for practical applications.
It is further another object of the invention to provide a chip-on-chip semiconductor device and a mounting method therefore.
A feature of the present invention is generally to provide marks such as an electrode mark, a back mark and an alignment mark on the back face of a semiconductor chip for recognition of the orientation of the semiconductor chip and the electrode arrangement on the semiconductor chip.
More specifically, (in accordance with an inventive aspect, there is provided a semiconductor chip for a chip-on-chip structure in which a plurality of semiconductor chips are bonded to one another in a stacked relation with electrode-carrying front faces thereof opposed to each other, the semiconductor chip comprising an electrode mark provided on a back face thereof in association with an electrode provided on a front face thereof.
In accordance with an inventive aspect, the semiconductor chip for the chip-on-chip structure according to claim
1
is characterized in that a plurality of electrodes are provided in a predetermined arrangement on the front face of the semiconductor chip, and a plurality of electrode marks are provided on the back face of the semiconductor chip in association with respective electrodes and in the same arrangement as the electrode arrangement.
In accordance with an inventive aspect, a semiconductor chip for a chip-on-chip structure is characterized in that a plurality of electrodes are provided in a predetermined arrangement on the front face of the semiconductor chip, and electrode marks are provided on the back face of the semiconductor chip in association with predetermined ones of the plurality of electrodes.
In accordance with an inventive aspect, there is provided a chip-on-chip semiconductor device which comprises a plurality of semiconductor chips bonded to one another in a stacked relation with electrode-carrying front faces thereof opposed to each other via electrodes provided on the opposed front faces, wherein electrode marks are provided on a back face of at least one of the stacked semiconductor chips in association with the electrodes on the front face of the one semiconductor chip.
In accordance with an inventive aspect, there is provided a chip-on-chip mounting method for stacking first and second semiconductor chips each having electrodes provided on a front face thereof so that the electrodes on the first semiconductor chip are bonded to the electrodes on the second semiconductor chip, the method comprising the steps of: placing the first semiconductor chip with the front face thereof upward; and positioning the second semiconductor chip with respect to the first semiconductor chip on the basis of electrode marks provided on a back face of the second semiconductor chip in association with the electrodes provided on the front face of the second semiconductor chip to mount the second semiconductor chip on the first semiconductor chip with the front face of the second semiconductor chip facing downward as opposed to the front face of the first semiconductor chip.
With the arrangements above, when the chip-on-chip structure is assembled with the front face of the semiconductor chip downward, the positioning of the semiconductor chip can be achieved on the basis of the electrode marks provided on the back face of the semiconductor chip. The electrode marks on the back face of the semiconductor chip are located in association with the electrodes on the front face of the semiconductor chip. The electrode marks provided in association with the electrodes may each be defined, for example, as a mark which surrounds an intersection between the back face and a phantom vertical line extending vertically through the semiconductor chip from an electrode. In other words, the electrode marks are each defined as a mark of an electrode as seen through the semiconductor chip from the back side thereof.
Therefore, with the electrode marks, the positions of the electrodes can be checked from the back side of the semiconductor chip, so that the semiconductor chip can properly be positioned with its face down in a desired position on another semiconductor chip to be bonded thereto. As a result, the chip-on-chip structure can be produced with almost no offset between the opposed electrodes. Since the positioning of the semiconductor chips is easy, the time required for assembling the chip-on-chip structure can be reduced.
Although the electrode marks are provided in association with respective electrodes, the electrode marks may be provided in association with specific ones of the electrodes for the purpose of the proper positioning of the semiconductor chip. For example, four electrode marks may be provided in association with electrodes disposed in four corners of the semiconductor chip.
With the arrangement according to one aspect of the instant invention, the chip-on-chip semiconductor device is provided in which the opposed electrodes are bonded to each other with a high level of precision, and the electrode positions of the semiconductor device can be checked. Further, it can be easily checked if the chip-on-chip semicond
Hikita Junichi
Kumamoto Nobuhisa
Nishimura Isamu
Yamamoto Koji
Pizarro-Crespo Marcos D.
Rader & Fishman & Grauer, PLLC
Rohm Co.,
Weiss Howard
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