Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1998-04-20
2001-02-20
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S529000, C257S778000
Reexamination Certificate
active
06191482
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a packaging technology for a semiconductor chip and, more particularly, to a semiconductor chip carrier and a semiconductor device using the same.
DESCRIPTION OF THE RELATED ART
A typical example of the semiconductor chip carrier
1
is illustrated in
FIGS. 1
to
4
. The prior art semiconductor chip carrier
1
comprises an insulating layer
2
a
and a conductive pattern
3
formed on an upper surface
2
b
of the insulating layer
2
a
. The insulating layer
2
a
is formed of synthetic resin such as polyimide, and through-holes
2
c
are formed in the insulting layer
2
a
. The upper surface
2
b
has a mounting area assigned to a semiconductor chip
4
and a peripheral area around the mounting area.
The conductive pattern
3
is formed of copper, and includes pads
3
a
, outer strips
3
b
, vertical connections
3
c
and a mesh sub-pattern
3
d
. The pads
3
a
are formed in the mounting area, and are connected to bumps
4
a
of the semiconductor chip
4
. The outer strips
3
b
extend from the pads
3
a
toward the through holes
2
c
, and are merged with the vertical connections
3
c
.The vertical connections
3
c
passes through the through-holes
2
c
, and are exposed to the lower surface
2
d
of the insulating layer
2
a
. The mesh sub-pattern
3
d
is formed in the mounting area
3
d
, and most of the conductive pattern
3
is covered with a protective layer
5
of solder resist or glass.
Synthetic resin is injected into the gap between the semiconductor chip
4
and the protective resin
5
, and forms a synthetic resin layer
6
. The conductive pattern
3
is 10 microns to 15 microns thick, and the protective layer
5
is 5 microns to 15 microns thick. The protective layer
5
on the conductive pattern
3
measures 30 microns high from the upper surface of the insulating resin layer
2
d
at the maximum, and the gap GP
1
between the protective layer
5
and the lower surface of the semiconductor chip
4
is only 0 to 15 microns. For this reason, while the manufacturer is injecting the melted synthetic resin into the space between the semiconductor chip carrier
1
and the lower surface of the semiconductor chip
4
, the melted synthetic resin
6
and filler
7
hardly flow through the narrow gap GP
1
, and void
8
takes place in the synthetic resin layer
6
as shown in
FIGS. 3 and 4
. The void
8
is causative of cracks, and the cracks deteriorate the prior art semiconductor device.
If the conductive pattern
3
is formed inside, the obstacle to the penetration is removed between the semiconductor chip carrier
1
and the semiconductor chip
4
. However, the semiconductor chip carrier loses a selecting function for disabling a certain circuit component of the integrated circuit. The conductive pattern
3
usually has a selecting sub-pattern, and the manufacturer selectively breaks the selecting sub-pattern by using a laser light radiation or a sand blustering. If the conductive pattern
3
is formed inside of the insulating layer
2
a
, it is not easy to disable a circuit component through the selective breakage of the selecting sub-pattern.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a semiconductor chip carrier, which allows sealant to smoothly flow into a gap under a semiconductor chip.
It is also an important object of the present invention to provide a semiconductor device, in which a semiconductor chip carrier is incorporated.
To accomplish the object, the present invention proposes to ensure that a conductive pattern is not present in a mounting area, except for pads to be bonded to a semiconductor chip.
In accordance with one aspect of the present invention, a semiconductor chip carrier for mounting a semiconductor chip is provided wich comprises an insulating layer, including a mounting area assigned to the semiconductor chip, and a peripheral area contiguous to the mounting area, and a conductive pattern including conductive pads exposed to the mounting area so as to be connected to conductive pieces of the semiconductor chip, a circuit sub-pattern electrically connected to the pads and assigned to the outside of the mounting area, except for a connecting portion merged with the pads and another sub-pattern formed in the peripheral area and evacuated from the mounting area.
In accordance with another aspect of the present invention, a semiconductor device comprising a semiconductor chip is provided on which a plurality of circuit components form an electric circuit, and a semiconductor chip carrier including an insulating layer including a mounting area assigned to the semiconductor chip and a peripheral area contiguous to the mounting area, and a conductive pattern including conductive pads exposed to the mounting area so as to be connected to conductive pieces of the semiconductor chip, a circuit sub-pattern electrically connected to the pads and assigned to the outside of the mounting area except for a connecting portion merged with the pads, and another sub-pattern formed in the peripheral area and not in the mounting area.
REFERENCES:
patent: 4847146 (1989-07-01), Yeh et al.
patent: 5541814 (1996-07-01), Janai et al.
patent: 5886877 (1999-03-01), Shingai et al.
patent: 1-289274 (1989-11-01), None
patent: 6-97229 (1994-04-01), None
Senba Naoji
Takahashi Nobuaki
Chaudhuri Olik
NEC Corporation
Wille Douglas A.
Young & Thompson
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