Semiconductor chip capable of supressing cracks in insulating la

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

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Details

257620, 257758, 257786, H01L 2358, H01L 23544, H01L 2348

Patent

active

057639361

ABSTRACT:
A resin molded semiconductor device having wiring layers and interlayer insulating layers inclusive of an SOG film, capable of suppressing generation of cracks in an SOG film to be caused by thermal stress. In the outer peripheral area of a semiconductor chip, via holes are formed in an interlayer insulating layer inclusive of an SOG film to substantially reduce residual SOG film. As an underlying layer of the interlayer insulating layer inclusive of the SOG film, dummy wiring patterns are formed to thin the SOG film on the dummy wiring patterns. Dummy wiring patterns may also be formed by using a higher level wiring layer, burying the via holes and contacting the lower level dummy wiring patterns.

REFERENCES:
patent: 4472730 (1984-09-01), Ohta
patent: 4949162 (1990-08-01), Tamaki et al.
patent: 5027188 (1991-06-01), Owada et al.
patent: 5117280 (1992-05-01), Adachi
patent: 5291066 (1994-03-01), Neugebauer et al.
patent: 5300814 (1994-04-01), Matsumoto et al.
patent: 5448112 (1995-09-01), Hara

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