Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
2000-12-15
2002-09-03
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S108000, C438S110000, C438S612000
Reexamination Certificate
active
06444489
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor chip assembly, and more particularly to a semiconductor chip assembly in which a semiconductor chip is attached to a molded substrate.
2. Description of the Related Art
Semiconductor chips have input/output pads that must be connected to external circuitry in order to function as part of an electronic system. The connection media is typically an array of metallic leads (e.g., a lead frame) or a support circuit (e.g., a substrate), although the connection can be made directly to a circuit panel (e.g., a mother board). Several connection techniques are widely used. These include wire bonding, tape automated bonding (TAB) and flip-chip bonding. Wire bonding is by far the most common. In this approach, wires are bonded, one at a time, from the chip to external circuitry by ultrasonic, thermocompression or thermosonic processes. TAB involves bonding gold-bumped pads on the chip to external circuitry on a polymer tape using thermocompression bonding. Both wire bonding and TAB require mechanical force such as pressure or a burst of ultrasonic vibration and elevated temperature to accomplish metallurgical welding between the wires or bumps and the designated surface.
Flip-chip bonding involves providing pre-formed solder bumps on the pads, flipping the chip so that the pads face down and are aligned with and contact matching bond sites, and melting the solder bumps to wet the pads and the bond sites. After the solder reflows it is cooled down and solidified to form solder joints between the pads and the bond sites. Organic conductive adhesive bumps with conductive fillers in polymer binders have been used in place of solder bumps, but they do not normally form a metallurgical interface in the classical sense. A major advantage of flip-chip bonding over wiring bonding and TAB is that it provides shorter connection paths between the chip and the external circuit, and therefore has better electrical characteristics such as less inductive noise, cross-talk, propagation delay and waveform distortion. In addition, flip-chip bonding requires minimal mounting area and weight which results in overall cost saving since no extra packaging and less circuit board space are used.
While flip chip technology has tremendous advantages over wire bonding and TAB, its cost and technical limitations are significant. For instance, the cost of forming bumps on the pads is significant. In addition, an adhesive is normally underfilled between the chip and the support circuit to reduce stress on the solder joints due to thermal mismatch between the chip and the support circuit, and the underfilling process increases both manufacturing complexity and cost. Furthermore, the solder joints exhibit increased electrical resistance as well as cracks and voids over time due to fatigue from thermo-mechanical stresses. Finally, the solder is typically a tin-lead alloy and lead-based materials are becoming far less popular due to environmental concerns over disposing of toxic materials and leaching of toxic materials into ground water supplies.
Other techniques besides wire bonding, TAB and flip-chip bonding have been developed to connect chips to external circuitry without using wires, leads or bumps. Such techniques include thin film rerouting at the wafer, panel or module level, and attaching a pre-patterned substrate to the chip such that through-holes in the substrate expose the pads and selectively applying conductive material into the through-holes.
Recent introduction of grid array packaging (e.g., ball grid arrays), chip size packages (CSP) and flip-chip packages using high density interconnect substrates are relentlessly driving increased printed circuit board density. Shrinking traces and spaces and increasing layer count increase printed circuit board density, however reducing the size of plated through-holes can even more significantly increase printed circuit board density. Small through-holes allow more routing space so that more conductive lines can be placed between the through-holes. Small through- holes also increase design flexibility and reduce design cycle time and overall product introduction time.
The semiconductor chip assembly is subsequently connected to another circuit such as a PCB or mother board during next level assembly. Different semiconductor assemblies are connected to the next level assembly in different ways. For instance, ball grid array (BGA) packages contain an array of solder balls, and land grid array (LGA) packages contain an array of metal pads that receive corresponding solder traces on the PCB. However, since BGA and LGA packages are connected to the PCB by solder joints, the compliance is small and solder joint reliability problems exist. Moreover, this lack of compliance can lead to loss of electrical contact. For instance, as the number of connections increase, the PCB becomes more prone to deform, and the accuracy of flatness and applied pressure becomes more difficult to meet. In addition, during operation, heat generated by the chip tends to create straining and warping due to differences in thermal coefficients of expansion in various materials. In order to reduce this problem, compliant bumps have been developed. Several approaches are described below.
U.S. Pat. No. 5,508,228 discloses a chip with compliant bumps over the pads for adhesive flip-chip assemblies. The compliant bumps include polymer bumps covered by a thin ductile metal layer. The compliant bumps are formed by depositing a polymeric material over the chip, selectively removing portions of the polymeric material so that polymer bumps remain over the pads, depositing a metal layer over the polymer bumps that electrically connects to the underlying pads, and severing the metal layer between adjacent bumps. Drawbacks to this approach include the difficulty with properly depositing the metal layer over the polymer bumps and the lack of horizontal routing (fan-in or fan-out) between the bumps and the pads.
U.S. Pat. No. 5,929,516 discloses a semiconductor chip assembly with a polymer substrate and a chip. The polymer substrate includes a polymer stud grid array that surrounds a trough and is formed by injection (or transfer) molding. Electrical conductors on the polymer substrate include outside terminals on the studs and inside terminals in or near the trough. The chip is disposed in the trough. In one embodiment, the chip is face-up and the pads are connected to the inside terminals near the trough by wire bonds. In another embodiment, the chip is face-down and the pads are connected to the inside terminals in the trough by solder joints in a flip-chip attachment. Drawbacks to this approach include the need to electrically connect the chip to the electrical conductors by wire bonds or solder joints, the inability to provide a chip size package and the inability to be manufactured during wafer processing.
In view of the various development stages and limitations in currently available semiconductor chip assemblies, there is a need for a semiconductor chip assembly that is cost-effective, reliable, manufacturable, provides excellent mechanical and electrical performance, and complies with stringent environmental standards.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor chip assembly with a semiconductor chip and a molded substrate that provides a low cost, high performance, high reliability package.
Another objective of the present invention is to provide a convenient, cost-effective method for manufacturing semiconductor chip assemblies as chip size packages, ball grid arrays or other structures.
In accordance with one aspect of the invention, a semiconductor chip assembly includes a chip and a molded substrate. The chip includes a conductive pad. The molded substrate includes a base, a bump that extends above the base, and a through-hole in the base that is offset from the bump and aligned with the pad. A routing line covers the bump, extends along a top surface
Picardat Kevin M.
Sigmond David M.
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