Semiconductor chip assembly and fabrication method therefor

Details Semiconductor chip assembly and fabrication method therefor Semiconductor chip assembly and fabrication method therefor

2005-12-28

2011-10-11

Im, Junghwa M (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Bump leads

C257S738000, C257S686000, C257SE23023, C438S109000, C438S108000, C438S112000

Reexamination Certificate

active

08035225

ABSTRACT:
A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly including a plurality of upper side pads (2a) provided on a substrate upper surface (1a); a plurality of lower side pads (2b) provided on a substrate lower surface (1b) corresponding to the upper side pads (2a) across the substrate (1), respectively; a first semiconductor chip (4) having first bumps (8a) joined to the upper side pads (2a), respectively; and a second semiconductor chip (5) having second bumps (8b) joined to the lower side pads (2b), respectively.

REFERENCES:
patent: 6677677 (2004-01-01), Kimura et al.
patent: 6966964 (2005-11-01), Nakamura et al.
patent: 2003/0060035 (2003-03-01), Kimura et al.
patent: 2003/0092326 (2003-05-01), Nishikawa et al.
patent: 2003/0138993 (2003-07-01), Nakamura et al.
patent: 2001 85605 (2001-03-01), None
patent: 2001 326322 (2001-11-01), None
patent: 2003 100801 (2003-04-01), None
patent: 2003 197853 (2003-07-01), None
English language Abstract of JP 2003-197853.
English language Abstract of JP 2001-326322.
English language Abstract of JP 2001-85605.
English language Abstract of JP 2003-100801.

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