Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2011-08-02
2011-08-02
Cox, Cassandra (Department: 2816)
Static information storage and retrieval
Interconnection arrangements
C327S419000
Reexamination Certificate
active
07990747
ABSTRACT:
There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch.
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International Search Report for PCT/JP2008/053612 mailed May 20, 2008.
Fukaishi Muneo
Hankui Eiji
Kuriyama Toshihide
Sasaki Hideki
Cox Cassandra
NEC Corporation
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