Semiconductor chip and semiconductor device

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C327S419000

Reexamination Certificate

active

07990747

ABSTRACT:
There are provided a semiconductor device and a semiconductor chip, in which the interconnection is made to be highly reliable by stacking three or more layers of chips without contact therebetween. A semiconductor chip of the present invention comprises a first signal transmission circuit, a silicon substrate on which a first changeover switch is formed, and an interconnection layer on which a first capacitive-coupling upper electrode is formed, wherein a first capacitive-coupling lower electrode is additionally formed on the rear surface of the silicon substrate through a first via hole that penetrates the silicon substrate and, whereas the first capacitive-coupling upper electrode is directly connected to the first signal transmission circuit, the first capacitive-coupling lower electrode is connected to the first signal transmission circuit through the first via hole and through the first changeover switch.

REFERENCES:
patent: 7738312 (2010-06-01), Shimano et al.
patent: 7906846 (2011-03-01), Hoshino et al.
patent: 2009/0065871 (2009-03-01), Lin et al.
patent: 56-002662 (1981-01-01), None
patent: 60-246654 (1985-12-01), None
patent: 62-020362 (1987-01-01), None
patent: 5-190770 (1993-07-01), None
patent: 8-241961 (1996-09-01), None
patent: 9-504908 (1997-05-01), None
patent: 2006019328 (2006-01-01), None
patent: 9966557 (1999-12-01), None
International Search Report for PCT/JP2008/053612 mailed May 20, 2008.

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