Semiconductor chip and semiconductor chip package comprising...

Details Semiconductor chip and semiconductor chip package comprising... Semiconductor chip and semiconductor chip package comprising...

2007-02-05

2008-09-02

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Interconnection arrangements

C365S189090, C365S226000

Reexamination Certificate

active

07420831

ABSTRACT:
Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal generating circuit electrically connected to first and second option pads. In the semiconductor chip, the chip selection signal generating circuit is enabled in accordance with a dual chip enable signal, and the control circuit is enabled and disabled in accordance with the chip selection signal received from the chip selection signal generating circuit. In addition, the chip selection signal generating circuit is adapted to generate a chip selection signal in accordance with signals received through the first and second option pads, respectively.

REFERENCES:
patent: 6115801 (2000-09-01), Rolandi
patent: 6366487 (2002-04-01), Yeom
patent: 2003/0122254 (2003-07-01), Lyne
patent: 2005/0152210 (2005-07-01), Park et al.
patent: 2004-150813 (2004-05-01), None
patent: 1020000045691 (2000-07-01), None
patent: 1020010097153 (2001-11-01), None
patent: 1020050067784 (2005-07-01), None

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