Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to nonconductive state
Reexamination Certificate
2006-02-03
2009-12-29
Jackson, Jr., Jerome (Department: 2815)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to nonconductive state
C438S467000, C438S601000, C257S529000, C257SE21314, C257SE21232
Reexamination Certificate
active
07638369
ABSTRACT:
There is provided a semiconductor chip having fuses. The semiconductor chip includes fuses each having a first terminal electrically connected to a first logic circuit, a second terminal electrically connected to a second logic circuit, and a blowable region formed between the first terminal and the second terminal; and fuse residues each having the same patterns with those of the first terminal and the second terminal of the fuses, and configured so that patterns corresponded to the first terminals and the second terminals are electrically disconnected from each other.
REFERENCES:
patent: 7312109 (2007-12-01), Madurawe
patent: 2004/0018711 (2004-01-01), Madurawe
patent: 2005/0181546 (2005-08-01), Madurawe
patent: WO 98/09327 (1998-03-01), None
K. Arndt et al., Reliability of Laser Activated Metal Fuses in DRAMs, 1999 IEEE/CPMT Int'l Electronics Manufacturing Technology Symposium, p. 389-394.
Kubota Ryo
Sakoh Takashi
Jackson, Jr. Jerome
NEC Electronics Corporation
Young & Thompson
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