Active solid-state devices (e.g. – transistors – solid-state diode – Physical configuration of semiconductor – With peripheral feature due to separation of smaller...
Reexamination Certificate
2000-09-05
2003-03-25
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Physical configuration of semiconductor
With peripheral feature due to separation of smaller...
C257S094000, C257S710000, C438S014000
Reexamination Certificate
active
06538302
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a semiconductor chip having a fracture sidewall running at a lateral edge region, and having an electrically active layer ending at the fracture sidewall. The invention furthermore relates to a method for fabricating such a semiconductor chip.
In semiconductor technology, semiconductor chips are fabricated in mass production in the so-called wafer composite. The finished individual semiconductor chips are then separated from one another. This is done by sawing or scribing and breaking along the resulting scribed track. In both cases, active layers running parallel to the surface of the semiconductor chip may end at these sawing or fracture sidewalls and thus be accessible.
It is often necessary to solder a semiconductor chip directly to a conductor. Added to this, specifically in the case of semiconductor laser chips (in particular in the case of so-called linear arrays of high-power lasers), is the fact that in these optoelectronic components, the active side (pn junction) must be mounted facing down (p-down mounting) in order to realize a voltage supply and/or a thermal heat dissipation. The spatial proximity of the active layer of the semiconductor laser chip to a contact area results here from the necessity of pumping the active layer and/or of dissipating the heat produced in the active layer. The active layer is thus situated directly over the contact layer arranged on the lower side. If such a component is then connected to a conductor, short circuits due to solder which touches the lateral fracture sidewall, and thus the active layer ending at the fracture sidewall, cannot be precluded, which can lead to the failure of the component.
The structure of a previous semiconductor laser chip is illustrated with reference to
FIG. 2. A
semiconductor chip
1
can be seen which has an active layer
2
formed in the semiconductor substrate, which active layer is assigned a contact area
3
and ends laterally at the side of the fracture sidewall
4
. The active layer
2
emerges at the fracture sidewall
4
within the scribed track
5
running in the direction of the fracture sidewall
4
. The scribed track
5
is required in order to break the semiconductor chip—originally situated in the wafer composite—along the fracture sidewall
4
, and thus to be able to separate it from the wafer composite. The contact area
3
applied on the underside of the semiconductor chip
1
is bounded by insulation layer regions
6
. The semiconductor chip
1
is soldered on the conductor
7
, which is of planar design, by means of a solder
8
. In practice, it often happens that the solder
8
rises up or forms a bead
9
at the fracture sidewalls of the semiconductor chip or else in the scribed tracks
5
, as illustrated by way of example in FIG.
3
. This can cause a short circuit of the active layer
2
with the conductor
7
and/or the contact area
3
, which may consequently entail a defect in the entire electronic circuit comprising the soldered-in semiconductor chip.
A previously known solution approach to this problem is shown in FIG.
3
. In this case, in order to avoid a short circuit, a comparatively complicated deep etching is provided in the region of a scribed track
5
, by means of which about 10 &mgr;m of the material of the semiconductor chip is removed in order to ensure that the end of the active layer
2
is covered by the insulation layer
6
, which is applied after the deep etching in the wafer composite. This deep etching leads to considerable costs and difficulties in the wafer process since all other regions of the semiconductor chips situated in the wafer composite have to be covered. Finally, even in spite of this expensive and complicated etching operation, with this type of semiconductor chips, short circuits of active layers with the solder have been observed.
The invention is based on the object of providing a semiconductor chip and a method for fabricating it in which a hazard to the semiconductor circuit through the formation of short circuits can be precluded in a structurally simple and therefore cost-effective manner.
This object is achieved by means of a semiconductor chip according to claim
1
and a method according to claim
6
.
According to the invention, at least one fracture-sidewall section which is assigned to the end of the active layer is provided with a passivation layer covering said section.
In this case, in a preferred embodiment of the invention, the passivation layer is formed by chemical conversion, in particular oxidation, of the starting material of the fracture sidewall and/or of that region of the active layer itself which ends at the fracture sidewall.
This oxidation is preferably carried out by means of a furnace process in the region of the fracture sidewall running at a lateral edge region. It is advantageous to carry out the oxidation in the furnace process through oxygen plasma or through water vapor at elevated temperature. It is advantageous in this case that no aqueous solution is used in the furnace process; the resulting electrically insulating passivation layer made of the oxidized semiconductor material therefore remains in the region of the fracture sidewall.
Further advantageous developments emerge from the subclaims.
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Völz, H.: “Elektronik” [Electronic], Akademie-Verlag, vol. 4, 1986, p. 230.
Beneking H.: “Halbleiter-Technologie” [Semiconductor Technology], B. G. Teubner, 1991, p.p. 408-409.
Greenberg Laurence A.
Mayback Gregory L.
Osram Opto Semiconductors GmbH
Stemer Werner H.
Tran Mai-Huong
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