Reexamination Certificate
2001-11-19
2003-06-24
Cuneo, Kamand (Department: 2829)
C257S620000
Reexamination Certificate
active
06582085
ABSTRACT:
RELATED APPLICATIONS
The present application is based upon Japanese Patent Application No. 2001-178533 which is entirely incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to a semiconductor chip and its manufacturing method. Also, the present invention relates to a silicon wafer for use in a process of manufacturing the semiconductor chip.
BACKGROUND OF THE INVENTION
Generally, according to a process for manufacturing semiconductor devices, a silicon wafer is formed with a number of chip portions divided by a number of street portions running and spacing between the neighboring chip portions. A conventional semiconductor manufacturing process is applied to the chip portions to produce semiconductor chips. The silicon wafer is then cut and separated by dicing along the street portions into small semiconductor chips. Each of the separated semiconductor chips is packaged and then provided to a final test in which features of the semiconductor chip are evaluated.
In addition to the final test, before being separated by dicing, each of the semiconductor chips is tested by the use of an associated electric circuit, i.e., test element group (TEG), formed on the neighboring street in order to detect any defect in the semiconductor chip. This prevents the defective semiconductor chips from not only being packaged but also being subject to the final test. Besides, in each of manufacturing processes, mask alignments are performed by the use of indications or marks provided on the streets.
For example, as shown in
FIG. 5A
the silicon wafer
500
is defined with a number of chip portions
502
defined by vertical and horizontal streets
504
. Also, as shown in
FIG. 5B
, a part of the street portion
504
positioned between the neighboring chip portions
502
bears an electric circuit such as resistor circuit
506
. The circuit
506
includes a pair of probe pads
508
and a resistance wire
510
running between the probe pads
508
, for example. In this circuit, an amount of resistance in the circuit
506
varies with a width and thickness of resistance wire formed therein. The size, i.e., width and thickness, of the resistance wire varies with a manufacturing precision of the semiconductor chips. This in turn means that the manufacturing precision of the regions adjacent to the circuit
506
can be evaluated from the amount of resistance of the wire
510
. In addition to the circuit
506
, an indication
512
is provided on the street portion which is used to determine a misalignment of each mask used in the manufacturing of the silicon wafer.
After the evaluation, the silicon wafer
500
is cut into semiconductor chips along centerlines of respective street portions
504
, which is illustrated in
FIGS. 6A-6C
. As can be seen from
FIG. 6A
, the probe pad
508
made of aluminum is supported on the street portion
504
through an insulation layer
501
provided between the street portion
504
and the probe pad
508
/ A dicer
514
, which is a notable diamond-cut disc, is used for cutting the silicon wafer
500
. In the drawing, respective parts of the street portion
504
, the probe pad
508
and insulation layer
501
, cut out by the dicer
514
, are defined between the dotted lines
516
. As shown in
FIG. 6B
, each bonding pad
518
on the separated semiconductor chip
513
including the chip portion and a remaining of the street portion
504
is connected with a corresponding terminal
520
on a package (not shown) through a bonding wire
522
extending in the form of arch between the bonding pad
518
and the terminal
520
.
Disadvantageously, as shown in
FIGS. 6B and 6C
, the dicing can result in a creation of burrs
524
at the cut edge of a remaining part
526
of the probe pad
508
. In this instance, as shown in
FIG. 6B
, if the wire
522
is extended as it draws a high arch, no physical contact would be made between the wire
522
and the burr
524
. Otherwise, as shown in
FIG. 6C
, the wire
522
makes a contact with the burr
524
, which results in an unwanted leakage of electric current. Also, the wire
522
is electrically connected to another wire through burrs and remaining parts
526
of the probe pads
508
, which results in a malfunction of the semiconductor chip.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide an improved semiconductor chip and silicone wafer, and a method for manufacturing the semiconductor, capable of eliminating or minimizing a creation of burrs.
To this end, a semiconductor chip which is manufactured by preparing a silicon wafer having a plurality of chip portions and a plurality of street portions each running and spacing between neighboring chip portions, each of the street portions bearing a circuit, and cutting out a central portion of each of the street portion by dicing while remaining either or both of end portions of the circuit adjacent to the chip portions, comprises a reinforcing portion, the reinforcing portion being provided on the circuit before the dicing and then cut out in part by dicing so that it remains in part on the remaining end portion of the circuit after dicing.
Also, a silicon wafer of the present invention has a plurality of chip portions, a plurality of street portions, each of the street portions running and spacing between neighboring chip portions, circuits provided on the street portions, and reinforcing portions. Each of the reinforcing portions is provided on each of the circuits before dicing and then cut out in part by dicing so that it remains in part on at least one end portion of the circuit, adjacent to the chip portions, after dicing.
Further, a method for manufacturing a semiconductor chip, comprises preparing a silicon wafer having a plurality of chip portions and a plurality of street portions each running and spacing between neighboring chip portions, each of the street portions bearing a circuit and a reinforcing portion on the circuit, and cutting out a central portion of each of the street portions by dicing while remaining at least one end portion of the circuit, adjacent to the chip portion, and the reinforcing portion on the one end portion of the circuit.
REFERENCES:
patent: 4890383 (1990-01-01), Lumbard et al.
patent: 5047711 (1991-09-01), Smith et al.
patent: 5477062 (1995-12-01), Natsume
patent: 5923047 (1999-07-01), Chia et al.
patent: 5942766 (1999-08-01), Frei
patent: 6121677 (2000-09-01), Song et al.
patent: 6291835 (2001-09-01), Tsuji et al.
patent: 6404217 (2002-06-01), Gordon
patent: 6410936 (2002-06-01), Hongo
patent: 6462401 (2002-10-01), Fujii
Cuneo Kamand
Geyer Scott B.
Mitsubishi Denki & Kabushiki Kaisha
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