Semiconductor characteristic evaluation apparatus

Details Semiconductor characteristic evaluation apparatus Semiconductor characteristic evaluation apparatus

2003-06-19

2004-12-21

Deb, Anjan (Department: 2858)

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

Reexamination Certificate

active

06833725

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-181459, filed Jun. 21, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor characteristic evaluation apparatus. More particularly, it relates to an element characteristic/circuit characteristic evaluation apparatus which evaluates a fluctuation of element characteristics or circuit characteristics in a semiconductor integrated circuit (hereinafter, referred to as an LSI (large scale integrated circuit)).
2. Description of the Related Art
In LSIs after a 0.1 &mgr;m generation, a fluctuation of element parameters must be taken into consideration, because an influence of the fluctuation of the element parameters becomes obvious, as the LSIs are more miniaturized and set to a lower voltage. In order to incorporate such a fluctuation of the element parameters into a design of the LSIs, it is necessary to accurately evaluate a fluctuation of element characteristics in an LSI chip, in a wafer surface, between wafers and between lots. Especially, the evaluation in the LSI chip is also important in order to accurately estimate a fluctuation of circuit characteristics of the entire LSI chip.
Conventionally, the characteristics of the elements have individually been measured for the fluctuation evaluation. For example, element evaluation patterns necessary for the measurement are all arranged on the chip to prepare an evaluation chip. Usually, the arrangement of the element evaluation patterns needs an area of about several hundred &mgr;m square. Accordingly, one or several chips are prepared, and all the element evaluation patterns are mounted thereon in accordance with the number of items to be measured. Then, during the measurement, the evaluation chips are mechanically moved in sequence to probe the individual element evaluation patterns.
Such a conventional method has the following drawbacks.
(1) Because of a large area of each element evaluation pattern, manufacturing costs of the evaluation chip become high. Additionally, since the element evaluation patterns are mounted on the chip in a wide range, it is difficult to distinguish a cause of a fluctuation correlation between elements from another, i.e., element characteristics from a difference in distances or positions on the chip.
(2) A layout of the evaluation chips is far apart from a normal LSI. That is, the evaluation chips are laid out where probe pads are bedded. Accordingly, the evaluation chips are manufactured under conditions different from original process tuning conditions. Therefore, there is a problem that an obtained result of measurement is not accurate reflection of a fluctuation of element characteristics in the real LSI.
(3) The measurement is accompanied by mechanical movement and mechanical contact by a probe. Accordingly, measuring time becomes considerable to increase evaluation costs. Additionally, since the mechanical contact is repeated by a number of times (several tens of thousands in some cases), errors easily occur due to a guarantee of stability and a fluctuation of contact resistance.
(4) The number of element evaluation patterns to be mounted on one evaluation chip is limited to several hundreds to several thousands. For the same element evaluation patterns, only several to several tens can be mounted on one evaluation chip. By such mounted numbers, it is impossible to carry out satisfactory statistical evaluation. Evaluation is carried out by measuring several tens of evaluation chips, but it is nothing more than average evaluation for a number of evaluation chips. Consequently, it is impossible to evaluate a difference among the evaluation chips, e.g., dependence on positions on the wafer.
(5) It is difficult to verify a correlation between obtained measurement data regarding the fluctuation of the element characteristics and the fluctuation of real circuit characteristics. A small volume of measurement data, a distance between the element evaluation patterns on the evaluation chip, and an inconsistent layout (e.g., a difference in pattern density or degree of miniaturization) are obstacles.
As against the aforementioned conventional method for mechanically moving the evaluation chips, there has been invented a method for electrically probing the element evaluation patterns, i.e., a method for electrically switching selection of patterns to be measured. In the case of this method, however, it has been considered that measurement accuracy necessary for evaluation cannot be secured due to an influence of an error caused by a leakage current of a changeover switch or a potential error caused by wiring resistance. Thus, the aforementioned method for mechanically moving the evaluation chips is still a mainstream evaluation apparatus.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor characteristic evaluation apparatus which can accurately evaluate a fluctuation of element characteristics and a fluctuation of circuit characteristics by electrically switching a measurement circuit system without any mechanical movement of an evaluation chip, and secure sufficient measurement accuracy necessary for evaluation.
According to a first aspect of the present invention, there is provided a semiconductor characteristic evaluation apparatus comprising a plurality of measurement units arranged on a chip, on which a plurality of measured patterns of components configuring a semiconductor integrated circuit and varying in kind from component to component are mounted; a measurement bus group arranged above the plurality of measurement units and connected to the plurality of measured patterns to configure a measurement circuit system in accordance with measured items of the components; a plurality of measurement pads, on the chip, which are arranged in a region other than an arrangement region of the plurality of measurement units and to which a measuring device is connected; a plurality of selection switches which select, in accordance with the measured items of the components, a measurement bus group configuring the measurement circuit system in accordance with the measured items and which connect the group to the plurality of measurement pads; and a control circuit which electrically controls switching of the plurality of selection switches in accordance with the measured items of the components.
According to the foregoing constitution, the components constituting the semiconductor integrated circuit mounted on the plurality of measurement units arranged on the chip are connected to the plurality of measured patterns varied in kind from component to component, whereby the connection between the measurement bus group constituting the measurement circuit system and the measurement pad in accordance with the measured items of the components is electrically controlled by the selection switch. The measurement bus group and the selection switch enable an optimal structure of the measurement circuit system and optimal application of a bias voltage. As a result, it is possible to prevent an influence of an error caused by leakage current of the changeover switch or a potential error caused by wiring resistance.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.


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Chen, J.C., et al., “An On-Chip, Interconnect Capacitance Character

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