Semiconductor chamber process apparatus and method

Adhesive bonding and miscellaneous chemical manufacture – Differential fluid etching apparatus – With means for passing discrete workpiece through plural...

Reexamination Certificate

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C156S345310, C118S719000, C414S935000

Reexamination Certificate

active

06802935

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor fabrication techniques and devices.
BACKGROUND OF THE INVENTION
In the semiconductor processing field, various process chambers can be utilized in association with a wafer handling system or device to perform a variety of semiconductor processes. These processes can include annealing, cleaning, chemical vapor deposition, oxidation, and nitridation. The processes may be applied under vacuum, under gas pressure and with the application of heat.
Semiconductor wafer processing systems comprised of multiple process chambers are well known in the art. Within these systems, wafers are generally prepared and processed through the deposition and treatment of multiple layers of conductive and semiconductive materials. Such tools process semiconductor wafers through a series of sequential steps to create integrated circuits. In such tools, a group of process chambers and preparatory chambers can be arranged in one or more clusters, each served by a robotic transfer mechanism. Hence, such tools are commonly referred to as cluster tools, which represent one type of wafer handling system or device currently in use. A commercially available example of a cluster tool is the Applied Materials Centura Platform (Applied Materials, 2881 Scott Boulevard, Santa Clara, Calif. 95050).
Chamber clusters within a cluster tool can be arranged by function with related functions located in separate clusters. For example, in some cluster tools utilized for metal deposition, there is a pre-metallization cluster where the wafers are admitted, oriented, degassed, sputter cleaned, subsequently cooled down and removed from the apparatus and at least one metallization cluster of process chambers wherein metal deposition, e.g., copper deposition, is performed. The various chambers of the pre-metallization cluster are serviced by a centrally located robotic transfer mechanism that is enclosed in a buffer chamber. Similarly, the process chambers of the process cluster are serviced by a centrally located robotic mechanism that is enclosed in a transfer chamber. Connecting these two clusters are transition chambers for moving the wafers between the metallization and pre-metallization clusters. These transition chambers are typically utilized for comparatively uncomplicated operations such as precleaning of the wafers prior to processing and cool down of the wafers after processing.
Regardless of whether semiconductor processing apparatus is configured as described above or in other arrangements known to those skilled in the art, it will be appreciated that the objective is simply to process the greatest number of wafers per unit of time in the most efficient manner. However, it is characteristic of all such apparatus that active chambers, i.e. those wherein semiconductor material is deposited or treated in some other manner, such as etching, must periodically be cleaned of the residues inherently formed during such procedures. It will further be appreciated that it is desirable to have as high a throughput as possible without sacrifice of the quality of the operation carried out in a deposition chamber before it must be cleaned.
Mechanical wafer handling systems transport wafers from wafer carriers to processing chambers and vice versa. Various fabrication processes are carried out in processing chambers, including annealing, oxidation, nitridation, etching, and deposition. The wafer handling system might include a robot, an arm operated by the robot, and an implement at the end of the arm to hold the wafer. To date, however, such wafer handling systems have been designed to include a single robot and the utilization of only four chambers. Additionally, such devices generally permit only two recipes to be combined into four processes. Every two processes are run in-situ at the same process chamber. Because of this design, different processes run in the same process chamber.
Thus, it is difficult to clean the chamber and particle performance becomes worse due to the lack of cleaning control thereof. Because of this particle issue, resulting semiconductor circuit device yields can be severely damaged. Thus, a need exists for an apparatus and method that can overcome the cleaning problems and particle issues associated with prior art wafer handling systems and devices, such as, for example, the Centura line of devices described earlier. The present inventors have designed a unique apparatus and method which can overcome these aforementioned problems.
BRIEF SUMMARY OF THE INVENTION
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
It is therefore an aspect of the present invention to provide an improved semiconductor processing apparatus and method.
It is another aspect of the present invention to provide an improved apparatus and method for cleaning one or more process chambers of a semiconductor processing apparatus.
It is yet another aspect of the present invention to provide an improved semiconductor processing apparatus and method wherein semiconductor processing operations are separated in different process chambers.
It is still another aspect of the present invention to provide an improved robot mechanism that operations in association with a semiconductor processing apparatus.
It is also an aspect of the present invention to prevent particle accumulation in process chambers utilized in semiconductor processing devices.
The above and other aspects of the present invention can thus be achieved as is now described. A semiconductor processing apparatus and method are disclosed herein, including a plurality of process chambers, wherein at least one semiconductor processing operation occurs within each process chamber among the plurality of process chambers. Additionally, the apparatus and method disclosed herein include a robot mechanism for rotating each process chamber among the plurality of process chambers upon completion of an associated semiconductor processing operation.
Such a robot mechanism may comprise a plurality of robots. Specifically, such a plurality of robots may include six robots configured on an associated carousel. Additionally a plurality of semiconductor processing operations can occur within the process chambers. The robot mechanism rotates each process chamber in a manner and a sequence for permitting the efficient cleaning of each process chamber and prevention of particle accumulation thereof.
A cleaning mechanism for cleaning a process chamber among the plurality of process chambers immediately following completion of a semiconductor processing operation within the process chamber may also be included. The plurality of process chambers can be comprise a first process chamber, a second process chamber, a third process chamber; a fourth process chamber; a sixth process chamber, and a seventh process chamber. The sixth process chamber may be configured as a multistage cooling chamber, while the seventh process chamber may be configured as a load lock chamber.
The robot mechanism may comprise a first robot associated with the first process chamber, a second robot associated with the second process chamber, a third robot associated with the third process chamber, a fourth robot associated with the fourth process chamber, a fifth robot associated with the multistage cooling chamber, and a sixth robot associated with the load lock chamber, wherein the first, second, third, fourth and fifth robots rotate on a carousel associated with the semiconductor processing apparatus.


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