Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2001-01-05
2002-09-03
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S758000, C257S773000
Reexamination Certificate
active
06445056
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to capacitor having a high dielectric withstanding voltage formed on a semiconductor substrate, and having a large capacitance formed within a small surface area.
2. Related Art
A capacitative element formed on a semiconductor device must achieve a large capacitance within a small region. To achieve this object, one method that is used is that of forming a capacitative element simultaneously with the formation of the usual MOS transistor. However, with advances in the shrinking of the design rule in semiconductor devices, the gate oxide film thickness has become thin, and if the above method is applied to form a capacitative element added for the purpose of achieving uniform pad terminal capacitances, the ESD (Electric Static Discharge) withstand voltage becomes low, and for this reason, there was a need to form a capacitative element having a sufficient degree of ESD withstanding voltage in a small surface area.
Accordingly, it is an object of the present invention, to improve on the above-noted drawbacks of the prior art, to provide a novel semiconductor device which enables the formation of capacitative element having ESD withstanding voltage in a small surface area.
SUMMARY OF THE INVENTION
In order to achieve the above-noted object, the present invention adopts the following basic technical constitution.
Specifically, the first aspect of a semiconductor device according to the present invention is a semiconductor device comprising: a first interconnect layer comprising a first electrode and a second electrode with a plurality of a tooth-shaped teeth and a connection portion for connecting the plurality of teeth, the first electrode and the second electrode being disposed in a mutually staggered fashion from opposite directions; a second interconnect layer comprising a third electrode and a fourth electrode with a plurality of tooth-shaped teeth and a connection portion for connecting the plurality of teeth, the third electrode and the fourth electrode being disposed in mutually staggered fashion from opposite directions; and an intervening interlayer disposed between the first interconnect layer and the second interconnect layer; wherein the teeth of the first electrode of the first interconnect layer overlap, via the intervening interlayer, with either teeth of the third electrode or teeth of the fourth electrode of the second interconnect layer, and the electrodes are connected so that potentials on the overlapping teeth are different, a capacitative element being formed by the four electrodes.
In the second aspect of the present invention, the electrodes of the first interconnect layer and the electrodes of the second interconnect layer are connected by contact holes provided in the connection portions in each of the electrodes.
In the third aspect of the present invention, a width of the teeth of the first electrode or the second electrode is different from a width of the teeth of the third electrode or the fourth electrode.
In the fourth aspect of the present invention, a width of the teeth of the first electrode or the second electrode is the same as a width of the third electrode or the fourth electrode.
In the fifth aspect of the present invention, a spacing between the teeth of the first electrode and the teeth of the second electrode is smaller than a spacing between the first electrode and the third electrode or the fourth electrode.
In the sixth aspect of the present invention, a spacing between the teeth of the third electrode and the teeth of the fourth electrode is smaller than a spacing between the first electrode and the third electrode or the fourth electrode.
The seventh aspect of the present invention is a semiconductor device comprising: a first interconnect layer comprising a first electrode and a second electrode with a plurality of a tooth-shaped teeth and a connection portion for connecting the plurality of teeth, the first electrode and the second electrode being disposed in a mutually staggered fashion from opposite directions; a second interconnect layer comprising a third electrode and a fourth electrode with a plurality of tooth-shaped teeth and a connection portion for connecting the plurality of teeth, the third electrode and the fourth electrode being disposed in mutually staggered fashion from opposite directions; and an intervening interlayer disposed between the first interconnect layer and the second interconnect layer; wherein the teeth of the first electrode of the first interconnect layer being disposed so as to overlap the teeth of the third electrode or the teeth of the fourth electrode of the second interconnect layer, via the intervening interlayer, and the electrodes of the first interconnect layer and the electrodes of the second interconnect layer are connected by a plurality of contact holes provided in each of the teeth of the electrodes, a capacitative element being formed by these four electrodes.
In the eighth aspect of the present invention, the electrodes of the first interconnect layer and the electrodes of the second layer are connected by contact holes provided in the each connect portion of the electrodes.
In the ninth aspect of the present invention, a spacing between the contact holes connecting the teeth of the first electrode and the teeth of the fourth electrode and the contact holes connecting the teeth of the second electrode and the teeth of the third electrode is smaller than a spacing between the first electrode and the third electrode or the fourth electrode.
REFERENCES:
patent: 5583359 (1996-12-01), Ng et al.
patent: 5789791 (1998-08-01), Bergemont
patent: 6100591 (2000-08-01), Ishii
patent: 61-263251 (1986-11-01), None
patent: 5-121207 (1993-05-01), None
patent: 7-297675 (1995-11-01), None
patent: 11-168173 (1999-06-01), None
Scully Scott Murphy & Presser
Wilson Allan R.
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