Measuring and testing – Instrument proving or calibrating
Reexamination Certificate
1999-11-19
2002-07-02
Williams, Hezron (Department: 2856)
Measuring and testing
Instrument proving or calibrating
C073S865900, C438S014000
Reexamination Certificate
active
06412326
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor calibration structures, semiconductor calibration wafers, calibration methods of calibrating semiconductor wafer coating systems, semiconductor processing methods of ascertaining layer alignment during processing, and calibration methods of calibrating multiple semiconductor wafer coating systems.
BACKGROUND OF THE INVENTION
During conventional applications of masking layers or photoresist layer coatings to semiconductor wafers, so-called coating systems are typically used. Such systems can include a flat, circular, disk-shaped, rotatable vacuum chuck having a diameter slightly less than that of a semiconductor wafer. The vacuum chuck can be used to hold and rotate a semiconductor wafer during application of the masking layer or photoresist. The vacuum chuck is typically oriented such that a semiconductor wafer placed thereon resides in a level horizontal plane. In operation, the bottom or inactive surface of a semiconductor wafer is placed on the vacuum chuck. The vacuum chuck applies a suction or negative pressure to the bottom surface of the semiconductor wafer to hold the semiconductor wafer thereon.
Typically, a desired amount of liquid photoresist is applied to the top, upwardly-facing surface of the semiconductor wafer, while the semiconductor wafer is being rotated on the vacuum chuck. Thus, as the semiconductor wafer is rotated, the photoresist material spreads radially outward from the center of the semiconductor wafer and toward the edge of the semiconductor wafer such that the entire top or active surface of the wafer is coated with a layer of photoresist. Excess photoresist material can be sloughed off the wafer during the rotation process. Excess amounts of photoresist, can, however, accumulate and form a mound or bead of photoresist on the outer edge of the semiconductor wafer. In order to eliminate the “edge bead” of photoresist, a coating system known as an edge bead removal unit can be employed.
Two types of edge bead removal units are well known in the art, chemical and optical. Chemical edge bead removal units include a nozzle which dispenses a solvent referred to as edge bead removal fluid, onto the photoresist at the edge of the semiconductor wafer. The solvent dissolves or develops away the photoresist and allows for easy removal of the photoresist from the edge of the semiconductor wafer. In an optical edge bead removal unit, the photoresist at or near the edge of the semiconductor wafer is exposed to light. During subsequent development processes, the exposed photoresist is removed. Photoresist which remains on the semiconductor wafer forms a mask for subsequent processing operations.
A problem which has arisen prior processes involves in inadvertent removing too much photoresist from the edge of semiconductor wafers thereby exposing substrate layers to undesirable etching operations. Another problem which has arisen in the context of the use of multiple coating systems, as is typical, is the inability to precisely control the amount of material removed as between these multiple coating systems.
Typically, several different edge bead removal units are utilized during fabrication of integrated circuit devices on semiconductor wafers. The use of different edge bead removal units commonly results in a random or haphazard stacking of substrate layers at or near the edge of the semiconductor wafer. The randomly or haphazardly stacked substrate layers can lift and detrimentally redeposit onto the semiconductor wafer. The redeposited substrate material can contaminate the semiconductor wafer and cause defects in the integrated circuit devices formed on the wafer. Additionally, random or haphazardly stacked layers at the edge of the semiconductor wafer often leave certain substrate layers detrimentally exposed to the ambient.
Furthermore, random or haphazard stacking of the substrate layers can also result in having a substrate layer inadvertently placed into contact with an underlying substrate layer to which the overlying layer will not stick. In such an instance, the overlying layer will tend to peel from the underlying layer and detrimentally redeposit onto the semiconductor wafer. For example, a metal layer placed directly on top of a polysilicon layer will often peel from the polysilicon layer, thereby contaminating the semiconductor wafer and causing defects in the integrated circuitry devices formed thereon. Methods of forming uniformly-stacked layers for reducing such edge-related defects are described in commonly-assigned U.S. Pat. No. 5,618,380, the disclosure of which is incorporated by reference herein.
This invention arose out of concerns associated with providing methods and structures for calibrating semiconductor processing equipment, and in particular, wafer coating systems.
SUMMARY OF THE INVENTION
Semiconductor wafer coating system calibration structures and methods are described. In one embodiment, a calibration structure includes a perimetral edge bounding a calibration body. A calibration edge is spaced from the perimetral edge and is positioned over the calibration body. Together, the edges define a distance therebetween which is configured to calibrate a wafer coating system. In a preferred embodiment, the edges define respective termination distances configured to calibrate multiple different wafer coating systems. In another embodiment, a calibration pattern is formed over a semiconductor wafer. A layer of material is formed over the calibration pattern by a coating system, and selected portions thereof removed by the system. The positions of unremoved portions of the layer of material are inspected relative to the calibration pattern to ascertain whether the coating system removed the selected portions within desired tolerances. If not, the coating system is calibrated to within desired tolerances.
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Hubbard Walter B.
Napolitano Lisa
Fayyaz Nashmiya
Philips Electronics North America Corp.
Williams Hezron
Zawilski P.
LandOfFree
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