Semiconductor buffer circuit with a transition delay circuit

Details Semiconductor buffer circuit with a transition delay circuit Semiconductor buffer circuit with a transition delay circuit

2001-08-13

2003-02-04

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Having specific delay in producing output waveform

C327S264000, C327S278000, C327S285000, C327S261000, C327S272000

Reexamination Certificate

active

06515529

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to input buffer circuits, and, more particularly, to a transition delay circuit for use in input buffer circuits.
2. Description of the Background
In a semiconductor device, it is desirable to include a buffer circuit which buffers the device input signals before they are communicated to the internal circuitry of the device. A buffer circuit typically adapts the device input signals to internally required signal properties, such as signal voltage levels and transition delays, that must be present for the internal circuitry to operate correctly.
FIG. 1
illustrates a prior art buffer
10
constructed using complementary metal oxide semiconductor (CMOS) technology. The buffer
10
is constructed as an inverter, with a p-type transistor
12
and an n-type transistor
14
. Input signal IN is input to the gate terminals of the transistor
12
and the transistor
14
. If the signal IN exceeds a threshold voltage value, the transistor
14
is turned “on” and output signal OUT has a path to ground through the transistor
14
. If the signal IN is below a certain threshold voltage value, the transistor
12
is turned “on” and the signal OUT is connected to VCC through the transistor
12
.
The buffer
10
in
FIG. 1
has the disadvantage that it is susceptible to noise and voltage surges. The buffer
10
has the further disadvantage that improper operation of the buffer
10
due to variations in operating conditions cannot be effectively corrected after the buffer
10
is constructed.
FIG. 2
illustrates a prior art buffer
16
that was designed to eliminate certain of the disadvantages of the buffer
10
of FIG.
1
. The buffer
16
is constructed of a series of inverter circuits
18
,
20
,
22
, and
24
which receive an input signal IN. A p-type MOS capacitor
26
is connected between VCC and the output of the inverter
22
. An n-type MOS capacitor is connected between the output of the inverter
22
and GND.
The inverters
18
,
20
, and
22
and the capacitors
26
and
28
comprise a delay circuit
30
. The MOS capacitors introduce a delay into the delay circuit
30
. When the input signal IN transitions from a high logic state to a low logic state, a node
29
, which is connected to the gate terminals of the capacitors
26
and
28
, transitions from a low logic state to a high logic state after a delay introduced by the inverters
18
,
20
, and
22
. As the node
29
transitions, the gate terminal of the n-type capacitor
26
pulls majority carriers (electrons) from the substrate causing capacitance to be formed. This capacitance introduces a delay into the delay circuit
30
.
When the input signal IN transitions from a low logic state to a high logic state, the node
29
transitions from a high logic state to a low logic state. As the node
29
transitions, the gate terminal of the p-type capacitor
28
pulls majority carriers (holes) from the substrate causing capacitance to be formed. This capacitance introduces a delay into the delay circuit
30
.
The MOS capacitors
26
and
28
provide for an adjustable delay in the delay circuit
30
because they may be “trimmed” of excess material to achieve the desired delay that is introduced by the capacitors
26
and
28
. The buffer
16
has the disadvantage that the delay, as measured by the time elapsed between the introduction of the input signal IN to the inverter
18
and the appearance of the output signal OUT at the output of the inverter
24
, associated with low to high transitions of the signal IN is not consistent with the delay associated with high to low transitions of the signal IN.
Thus, the need exists for a transition delay circuit that may be incorporated into a buffer to provide similar low to high and high to low input transition delay times.
SUMMARY OF THE INVENTION
The present invention, according to its broadest implementation, is directed to a transition delay circuit which includes a delay circuit that is responsive to an input signal. The delay circuit produces an output signal at a common node. The transition delay circuit also includes a first MOS capacitor connected between the input signal and the common node and a second MOS capacitor connected between the input signal and the common node.
The present invention also contemplates a buffer circuit which includes a transition delay circuit and an inverter responsive to the transition delay circuit. A semiconductor device comprising a plurality of buffer circuits having transition delay circuits and a functional circuit responsive to the buffer circuit is also disclosed.
The present invention further contemplates a system which includes a processor having at least one buffer circuit, a memory controller having at least one buffer circuit, a plurality of memory devices, each having at least one buffer circuit, a first bus connecting the processor and the memory controller, and a second bus connecting the memory controller and the memory devices. The buffer circuits include a transition delay circuit and an inverter responsive to the transition delay circuit.
The present invention also contemplates a method for delaying an input signal to a buffer circuit. The method includes the steps of inputting the input signal to a delay circuit and two MOS capacitors. One of the MOS capacitors is charged to produce a delayed signal and the delayed signal is outputted.
The present invention represents a substantial advance over prior buffers. Because the present invention has a feed-forward transition delay circuit, the low to high and high to low transitions of the input signal have approximately the same delays as measured from the time the transitioning input signal is introduced to the buffer and the time the signal appears at the output of the buffer. This unexpected advantage, and other advantages and benefits of the present invention, will become apparent from the Detailed Description of the Preferred Embodiments hereinbelow.


REFERENCES:
patent: 5343086 (1994-08-01), Fung et al.
patent: 5459424 (1995-10-01), Hattori
patent: 5517131 (1996-05-01), Tien et al.
patent: 5920221 (1999-07-01), Shen et al.
patent: 6154078 (2000-11-01), Stave
patent: 07058591 (1995-03-01), None
Morgan, “Get a Controlled Delay and Ramp with a Single CMOS Inverter Package,”Electronic Design,7 vol. 26, Mar. 29, 1978.

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