Semiconductor buffer circuit using enhancement-mode, depletion-m

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307450, 307481, 365230, H03K 19096, G11C 800

Patent

active

045047464

ABSTRACT:
An address buffer circuit is provided which has first and second MOS transistors whose current paths are connected in series with each other and whose gates are supplied with input signals of opposite phases, and third and fourth MOS transistors whose current paths are connected in series with each other. The first and third MOS transistors are of I-type. The gate of the third MOS transistor is connected to a junction of the first and second MOS transistors and the gates of the second and fourth MOS transistors are commonly connected. The address buffer circuit further has a MOS transistor which controls the conduction state of the third MOS transistor in response to an external control signal.

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patent: 4247921 (1981-01-01), Itoh et al.
patent: 4296339 (1981-10-01), Murotani
patent: 4300213 (1981-11-01), Tanimura et al.
patent: 4384220 (1983-05-01), Segawa et al.
patent: 4408305 (1983-10-01), Kuo

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